[coreboot-gerrit] Patch set updated for coreboot: c039475 Intel BD82x6x: LPC: Unify I/O APIC setup

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183

-gerrit

commit c039475cb0edd74dd61f67376303bb850137eaf7
Author: Paul Menzel 
Date:   Fri May 3 12:23:39 2013 +0200

Intel BD82x6x: LPC: Unify I/O APIC setup

Remove local copies of reading and writing I/O APIC registers by
    using already available functions.

This change is similar to

commit db4f875a412e6c41f48a86a79b72465f6cd81635
        Author: Kyösti Mälkki 
        Date:   Tue Jan 31 17:24:12 2012 +0200

IOAPIC: Divide setup_ioapic() in two parts.

Reviewed-on: http://review.coreboot.org/300

and

commit e614353194c712a40aa8444a530b2062876eabe3
        Author: Kyösti Mälkki 
        Date:   Tue Feb 26 17:24:41 2013 +0200

Unify setting 82801a/b/c/d IOAPIC ID

Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too. Define
    `ACPI_EN` in the header file `pch.h`.

As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
    not needed: “The existing code path *in this file* is about enabling
    the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c
    Signed-off-by: Paul Menzel 
---
 src/southbridge/intel/bd82x6x/lpc.c | 48 +++++++++++++------------------------
 src/southbridge/intel/bd82x6x/pch.h |  1 +
 2 files changed, 18 insertions(+), 31 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 7bcadc9..e052150 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -39,43 +39,29 @@

typedef struct southbridge_intel_bd82x6x_config config_t;

-static void pch_enable_apic(struct device *dev)
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void pch_enable_ioapic(struct device *dev)
 {
-	int i;
    u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);

-	/* Enable ACPI I/O and power management.
-	 * Set SCI IRQ to IRQ9
-	 */
-	pci_write_config8(dev, ACPI_CNTL, 0x80);
+	/* Enable ACPI I/O range decode */
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);

-	*ioapic_index = 0;
-	*ioapic_data = (2 << 24);
+	set_ioapic_id(IO_APIC_ADDR, 0x02);

/* affirm full set of redirection table entries ("write once") */
-	*ioapic_index = 1;
-	reg32 = *ioapic_data;
-	*ioapic_index = 1;
-	*ioapic_data = reg32;
-
-	*ioapic_index = 0;
-	reg32 = *ioapic_data;
-	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
-	if (reg32 != (2 << 24))
-		die("APIC Error\n");
-
-	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
-	for (i=0; i<3; i++) {
-		*ioapic_index = i;
-		printk(BIOS_SPEW, "  reg 0x%04x:", i);
-		reg32 = *ioapic_data;
-		printk(BIOS_SPEW, " 0x%08x\n", reg32);
-	}
+	reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+	io_apic_write(IO_APIC_ADDR, 0x01, reg32);

-	*ioapic_index = 3; /* Select Boot Configuration register. */
-	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+	/*
+	 * Select Boot Configuration register (0x03) and
+	 * use Processor System Bus (0x01) to deliver interrupts.
+	 */
+	io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
 }

static void pch_enable_serial_irqs(struct device *dev)
@@ -538,7 +524,7 @@ static void lpc_init(struct device *dev)
    pci_write_config16(dev, PCI_COMMAND, 0x000f);

/* IO APIC initialization. */
-	pch_enable_apic(dev);
+	pch_enable_ioapic(dev);

pch_enable_serial_irqs(dev);

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7f64571..1137a6e 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -119,6 +119,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);

#define PMBASE			0x40
 #define ACPI_CNTL		0x44
+#define   ACPI_EN		(1 << 7)
 #define BIOS_CNTL		0xDC
 #define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */