the following patch was just integrated into master: commit 72a42886505f54e81f437b618af1ab57e95c4b71 Author: David Hendricks dhendrix@chromium.org Date: Fri Aug 23 15:25:07 2013 -0700
exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420
This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte.
Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now.
This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See http://crosbug.com/p/20577.
This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks dhendrix@chromium.org
Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks dhendrix@chromium.org Tested-by: David Hendricks dhendrix@chromium.org Reviewed-by: ron minnich rminnich@chromium.org (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins)
See http://review.coreboot.org/6612 for details.
-gerrit