Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yu-Ping Wu.
Mengqi Zhang has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
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Patch Set 11:
(1 comment)
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/4b8246ad_a5a20ac3?usp... :
PS9, Line 432: host->src_hz = 400 * 1000 * 1000;
Mengqi will reply later.
When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and the frequency division value to 125. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set the source clock frequency correctly, we can get the correct frequency division value, and then get the correct clock output. The related code is https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thir...
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