build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44730 )
Change subject: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time ......................................................................
Patch Set 1:
(9 comments)
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_dvfs.c:
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 41: PERFCTL0_EMILLATEN, (perfctl0_bak >>1) & 0x1); need consistent spacing around '>>' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 59: } while(ack_state != complete); space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 197: dramc_dbg("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 199: dramc_dbg("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 269: SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 280: SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 285: SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 289: for (u8 chn = 0; chn < CHANNEL_MAX; chn++) suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/44730/1/src/soc/mediatek/mt8192/dra... PS1, Line 290: SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0); line over 96 characters