Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 98:
(1 comment)
File src/soc/intel/pantherlake/acpi/pcie.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/ec3cdc96_c95daf15?usp... :
PS81, Line 269: Device (RP11)
: {
: Name (_ADR, 0x00060002)
:
: OperationRegion (RPCS, PCI_Config, 0x4c, 4)
: Field (RPCS, AnyAcc, NoLock, Preserve)
: {
: , 24,
: RPPN, 8, /* Root Port Number */
: }
:
: Method (_PRT)
: {
: Return (IRQM (RPPN))
: }
: }
:
: Device (RP12)
: {
: Name (_ADR, 0x00060003)
:
: OperationRegion (RPCS, PCI_Config, 0x4c, 4)
: Field (RPCS, AnyAcc, NoLock, Preserve)
: {
: , 24,
: RPPN, 8, /* Root Port Number */
: }
:
: Method (_PRT)
: {
: Return (IRQM (RPPN))
: }
don't you need SoC Kconfig guard for PTL-H that has 10 PCIe RPs?
Done
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