Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42513 )
Change subject: tigerlake: enable tcc_offset functionality ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42513/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42513/3/src/mainboard/google/voltee... PS3, Line 208: 10
Or was the issue not the actual heat itself causing SoC hang issues but the fact that power was bein […]
Current Temperature Target (TjMax) is 100 degree C as per bits [23:16]. Above we are setting TCC Target Offset to 10 degree C [bits 30:24]. So, Pcode FW will start taking throttling action at 90 degree C [i.e. Temperature Target - Offset]. If there is no Target Offset (i.e. suppose 0) than FW will start throttling action at 100 degree C which is very high temperature and might be late to take any thermal throttling action to control the temperature. Here, by setting Target Offset to 10 degree C will prevent SoC temperature to rise above 90 degree C and help to control thermal heat up issues by taking early thorttling action.