[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#

[Rizwan Qureshi (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Nico Huber, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31445

to look at the new patch set (#15).

Change subject: soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#
......................................................................

soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#

SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.

However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.

Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.

Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.

BUG=b:123350329

Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/acpi/scs.asl
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
4 files changed, 32 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31445/15