Patrick Georgi (patrick@georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6662
-gerrit
commit b238bca05ac07260e287509a73123218920e53f9 Author: Patrick Georgi patrick@georgi-clan.de Date: Thu Aug 14 18:50:58 2014 +0200
unify romstage entry point
It's all the same now, with a single definition to satisfy C standard's "freestanding" requirements in a sane way.
Change-Id: Ibf51db9cdae36cb6e41d8f8e6df2f992c7cc3ed9 Signed-off-by: Patrick Georgi patrick@georgi-clan.de --- src/arch/armv7/include/arch/stages.h | 2 -- src/cpu/amd/agesa/cache_as_ram.inc | 2 +- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/include/cpu/amd/car.h | 1 - src/include/cpu/intel/car.h | 7 ------- src/include/stdlib.h | 2 ++ src/mainboard/a-trend/atc-6220/romstage.c | 5 ++--- src/mainboard/a-trend/atc-6240/romstage.c | 5 ++--- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 5 ++--- src/mainboard/abit/be6-ii_v2_0/romstage.c | 5 ++--- src/mainboard/advansus/a785e-i/romstage.c | 4 +++- src/mainboard/advantech/pcm-5820/romstage.c | 5 ++--- src/mainboard/amd/bimini_fam10/romstage.c | 4 +++- src/mainboard/amd/db800/romstage.c | 5 ++--- src/mainboard/amd/dbm690t/romstage.c | 4 +++- src/mainboard/amd/dinar/romstage.c | 4 +++- src/mainboard/amd/inagua/romstage.c | 4 +++- src/mainboard/amd/mahogany/romstage.c | 4 +++- src/mainboard/amd/mahogany_fam10/romstage.c | 4 +++- src/mainboard/amd/norwich/romstage.c | 5 ++--- src/mainboard/amd/olivehill/romstage.c | 4 +++- src/mainboard/amd/parmer/romstage.c | 4 +++- src/mainboard/amd/persimmon/romstage.c | 4 +++- src/mainboard/amd/pistachio/romstage.c | 4 +++- src/mainboard/amd/rumba/romstage.c | 5 ++--- src/mainboard/amd/serengeti_cheetah/romstage.c | 4 +++- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 4 +++- src/mainboard/amd/south_station/romstage.c | 4 +++- src/mainboard/amd/thatcher/romstage.c | 4 +++- src/mainboard/amd/tilapia_fam10/romstage.c | 4 +++- src/mainboard/amd/torpedo/romstage.c | 4 +++- src/mainboard/amd/union_station/romstage.c | 4 +++- src/mainboard/aopen/dxplplusu/romstage.c | 5 ++--- src/mainboard/arima/hdama/romstage.c | 4 +++- src/mainboard/artecgroup/dbe61/romstage.c | 5 ++--- src/mainboard/asi/mb_5blgp/romstage.c | 5 ++--- src/mainboard/asi/mb_5blmp/romstage.c | 5 ++--- src/mainboard/asrock/939a785gmh/romstage.c | 4 +++- src/mainboard/asrock/e350m1/romstage.c | 4 +++- src/mainboard/asrock/imb-a180/romstage.c | 4 +++- src/mainboard/asus/a8n_e/romstage.c | 4 +++- src/mainboard/asus/a8v-e_deluxe/romstage.c | 4 +++- src/mainboard/asus/a8v-e_se/romstage.c | 4 +++- src/mainboard/asus/dsbf/romstage.c | 5 ++--- src/mainboard/asus/f2a85-m/romstage.c | 4 +++- src/mainboard/asus/k8v-x/romstage.c | 4 +++- src/mainboard/asus/m2n-e/romstage.c | 4 +++- src/mainboard/asus/m2v-mx_se/romstage.c | 4 +++- src/mainboard/asus/m2v/romstage.c | 4 +++- src/mainboard/asus/m4a78-em/romstage.c | 4 +++- src/mainboard/asus/m4a785-m/romstage.c | 4 +++- src/mainboard/asus/m5a88-v/romstage.c | 4 +++- src/mainboard/asus/mew-am/romstage.c | 5 ++--- src/mainboard/asus/mew-vm/romstage.c | 5 ++--- src/mainboard/asus/p2b-d/romstage.c | 5 ++--- src/mainboard/asus/p2b-ds/romstage.c | 5 ++--- src/mainboard/asus/p2b-f/romstage.c | 5 ++--- src/mainboard/asus/p2b-ls/romstage.c | 5 ++--- src/mainboard/asus/p2b/romstage.c | 5 ++--- src/mainboard/asus/p3b-f/romstage.c | 5 ++--- src/mainboard/avalue/eax-785e/romstage.c | 4 +++- src/mainboard/axus/tc320/romstage.c | 5 ++--- src/mainboard/azza/pt-6ibd/romstage.c | 5 ++--- src/mainboard/bachmann/ot200/romstage.c | 5 ++--- src/mainboard/bcom/winnet100/romstage.c | 5 ++--- src/mainboard/bcom/winnetp680/romstage.c | 5 ++--- src/mainboard/bifferos/bifferboard/romstage.c | 3 +-- src/mainboard/biostar/m6tba/romstage.c | 5 ++--- src/mainboard/broadcom/blast/romstage.c | 4 +++- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 5 ++--- src/mainboard/cubietech/cubieboard/romstage.c | 2 +- src/mainboard/digitallogic/adl855pc/romstage.c | 5 ++--- src/mainboard/digitallogic/msm586seg/romstage.c | 5 ++--- src/mainboard/digitallogic/msm800sev/romstage.c | 5 ++--- src/mainboard/dmp/vortex86ex/romstage.c | 5 ++--- src/mainboard/eaglelion/5bcm/romstage.c | 5 ++--- src/mainboard/ecs/p6iwp-fe/romstage.c | 5 ++--- src/mainboard/emulation/qemu-armv7/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/romstage.c | 5 ++--- src/mainboard/emulation/qemu-q35/romstage.c | 5 ++--- src/mainboard/getac/p470/romstage.c | 5 ++--- src/mainboard/gigabyte/ga-6bxc/romstage.c | 5 ++--- src/mainboard/gigabyte/ga-6bxe/romstage.c | 5 ++--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 4 +++- src/mainboard/gigabyte/m57sli/romstage.c | 4 +++- src/mainboard/gigabyte/ma785gm/romstage.c | 4 +++- src/mainboard/gigabyte/ma785gmt/romstage.c | 4 +++- src/mainboard/gigabyte/ma78gm/romstage.c | 4 +++- src/mainboard/gizmosphere/gizmo/romstage.c | 4 +++- src/mainboard/google/butterfly/romstage.c | 5 ++--- src/mainboard/google/link/romstage.c | 5 ++--- src/mainboard/google/parrot/romstage.c | 5 ++--- src/mainboard/google/pit/romstage.c | 2 +- src/mainboard/google/snow/romstage.c | 2 +- src/mainboard/google/stout/romstage.c | 5 ++--- src/mainboard/hp/dl145_g1/romstage.c | 4 +++- src/mainboard/hp/dl145_g3/romstage.c | 4 +++- src/mainboard/hp/dl165_g6_fam10/romstage.c | 4 +++- src/mainboard/hp/e_vectra_p2706t/romstage.c | 5 ++--- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 +++- src/mainboard/ibase/mb899/romstage.c | 5 ++--- src/mainboard/ibm/e325/romstage.c | 4 +++- src/mainboard/ibm/e326/romstage.c | 4 +++- src/mainboard/iei/juki-511p/romstage.c | 5 ++--- src/mainboard/iei/kino-780am2-fam10/romstage.c | 4 +++- src/mainboard/iei/nova4899r/romstage.c | 5 ++--- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 5 ++--- src/mainboard/iei/pm-lx-800-r11/romstage.c | 5 ++--- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 5 ++--- src/mainboard/intel/cougar_canyon2/romstage.c | 3 ++- src/mainboard/intel/d810e2cb/romstage.c | 5 ++--- src/mainboard/intel/d945gclf/romstage.c | 5 ++--- src/mainboard/intel/eagleheights/romstage.c | 5 ++--- src/mainboard/intel/emeraldlake2/romstage.c | 5 ++--- src/mainboard/intel/jarrell/romstage.c | 5 ++--- src/mainboard/intel/mtarvon/romstage.c | 5 ++--- src/mainboard/intel/truxton/romstage.c | 5 ++--- src/mainboard/intel/xe7501devkit/romstage.c | 6 ++---- src/mainboard/iwave/iWRainbowG6/romstage.c | 5 ++--- src/mainboard/iwill/dk8_htx/romstage.c | 4 +++- src/mainboard/iwill/dk8s2/romstage.c | 4 +++- src/mainboard/iwill/dk8x/romstage.c | 4 +++- src/mainboard/jetway/j7f2/romstage.c | 5 ++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 4 +++- src/mainboard/jetway/pa78vm5/romstage.c | 4 +++- src/mainboard/kontron/986lcd-m/romstage.c | 5 ++--- src/mainboard/kontron/kt690/romstage.c | 4 +++- src/mainboard/kontron/ktqm77/romstage.c | 5 ++--- src/mainboard/lanner/em8510/romstage.c | 5 ++--- src/mainboard/lenovo/t520/romstage.c | 5 ++--- src/mainboard/lenovo/t530/romstage.c | 5 ++--- src/mainboard/lenovo/t60/romstage.c | 5 ++--- src/mainboard/lenovo/x200/romstage.c | 3 ++- src/mainboard/lenovo/x201/romstage.c | 5 ++--- src/mainboard/lenovo/x230/romstage.c | 5 ++--- src/mainboard/lenovo/x60/romstage.c | 5 ++--- src/mainboard/lippert/frontrunner-af/romstage.c | 4 +++- src/mainboard/lippert/frontrunner/romstage.c | 5 ++--- src/mainboard/lippert/hurricane-lx/romstage.c | 5 ++--- src/mainboard/lippert/literunner-lx/romstage.c | 5 ++--- src/mainboard/lippert/roadrunner-lx/romstage.c | 5 ++--- src/mainboard/lippert/spacerunner-lx/romstage.c | 5 ++--- src/mainboard/lippert/toucan-af/romstage.c | 4 +++- src/mainboard/mitac/6513wu/romstage.c | 5 ++--- src/mainboard/msi/ms6119/romstage.c | 5 ++--- src/mainboard/msi/ms6147/romstage.c | 5 ++--- src/mainboard/msi/ms6156/romstage.c | 5 ++--- src/mainboard/msi/ms6178/romstage.c | 5 ++--- src/mainboard/msi/ms7135/romstage.c | 4 +++- src/mainboard/msi/ms7260/romstage.c | 4 +++- src/mainboard/msi/ms9185/romstage.c | 4 +++- src/mainboard/msi/ms9282/romstage.c | 4 +++- src/mainboard/msi/ms9652_fam10/romstage.c | 4 +++- src/mainboard/nec/powermate2000/romstage.c | 5 ++--- src/mainboard/newisys/khepri/romstage.c | 4 +++- src/mainboard/nokia/ip530/romstage.c | 5 ++--- src/mainboard/nvidia/l1_2pvv/romstage.c | 4 +++- src/mainboard/packardbell/ms2290/romstage.c | 5 ++--- src/mainboard/pcengines/alix1c/romstage.c | 5 ++--- src/mainboard/pcengines/alix2d/romstage.c | 5 ++--- src/mainboard/rca/rm4100/romstage.c | 5 ++--- src/mainboard/roda/rk886ex/romstage.c | 5 ++--- src/mainboard/roda/rk9/romstage.c | 5 ++--- src/mainboard/samsung/lumpy/romstage.c | 5 ++--- src/mainboard/samsung/stumpy/romstage.c | 5 ++--- src/mainboard/siemens/sitemp_g1p1/romstage.c | 4 +++- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 5 ++--- src/mainboard/sunw/ultra40/romstage.c | 4 +++- src/mainboard/supermicro/h8dme/romstage.c | 4 +++- src/mainboard/supermicro/h8dmr/romstage.c | 4 +++- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 4 +++- src/mainboard/supermicro/h8qgi/romstage.c | 4 +++- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 +++- src/mainboard/supermicro/h8scm/romstage.c | 4 +++- src/mainboard/supermicro/h8scm_fam10/romstage.c | 4 +++- src/mainboard/supermicro/x6dai_g/romstage.c | 5 ++--- src/mainboard/supermicro/x6dhe_g/romstage.c | 5 ++--- src/mainboard/supermicro/x6dhe_g2/romstage.c | 5 ++--- src/mainboard/supermicro/x6dhr_ig/romstage.c | 5 ++--- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 5 ++--- src/mainboard/supermicro/x7db8/romstage.c | 5 ++--- src/mainboard/technexion/tim5690/romstage.c | 4 +++- src/mainboard/technexion/tim8690/romstage.c | 4 +++- src/mainboard/technologic/ts5300/romstage.c | 5 ++--- src/mainboard/televideo/tc7020/romstage.c | 5 ++--- src/mainboard/thomson/ip1000/romstage.c | 5 ++--- src/mainboard/ti/beaglebone/romstage.c | 2 +- src/mainboard/traverse/geos/romstage.c | 5 ++--- src/mainboard/tyan/s1846/romstage.c | 5 ++--- src/mainboard/tyan/s2735/romstage.c | 5 ++--- src/mainboard/tyan/s2850/romstage.c | 4 +++- src/mainboard/tyan/s2875/romstage.c | 4 +++- src/mainboard/tyan/s2880/romstage.c | 4 +++- src/mainboard/tyan/s2881/romstage.c | 4 +++- src/mainboard/tyan/s2882/romstage.c | 4 +++- src/mainboard/tyan/s2885/romstage.c | 4 +++- src/mainboard/tyan/s2891/romstage.c | 4 +++- src/mainboard/tyan/s2892/romstage.c | 4 +++- src/mainboard/tyan/s2895/romstage.c | 4 +++- src/mainboard/tyan/s2912/romstage.c | 4 +++- src/mainboard/tyan/s2912_fam10/romstage.c | 4 +++- src/mainboard/tyan/s4880/romstage.c | 4 +++- src/mainboard/tyan/s4882/romstage.c | 4 +++- src/mainboard/tyan/s8226/romstage.c | 4 +++- src/mainboard/via/epia-cn/romstage.c | 5 ++--- src/mainboard/via/epia-m/romstage.c | 5 ++--- src/mainboard/via/epia-m700/romstage.c | 6 ++---- src/mainboard/via/epia-m850/romstage.c | 6 ++---- src/mainboard/via/epia-n/romstage.c | 5 ++--- src/mainboard/via/epia/romstage.c | 5 ++--- src/mainboard/via/pc2500e/romstage.c | 5 ++--- src/mainboard/via/vt8454c/romstage.c | 5 ++--- src/mainboard/winent/mb6047/romstage.c | 4 +++- src/mainboard/winent/pl6064/romstage.c | 5 ++--- src/mainboard/wyse/s50/romstage.c | 5 ++--- src/northbridge/via/vx800/examples/chipset_init.c | 2 +- src/northbridge/via/vx800/examples/romstage.c | 3 ++- src/soc/intel/fsp_baytrail/romstage/romstage.c | 3 ++- src/southbridge/intel/fsp_rangeley/romstage.c | 3 ++- 219 files changed, 512 insertions(+), 453 deletions(-)
diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/armv7/include/arch/stages.h index 671c02b..0008039 100644 --- a/src/arch/armv7/include/arch/stages.h +++ b/src/arch/armv7/include/arch/stages.h @@ -20,8 +20,6 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H
-extern void main(void); - void stage_entry(void) __attribute__((section(".text.stage_entry.armv7"))); void stage_exit(void *);
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 449cf69..8fc69c3 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -76,7 +76,7 @@ cache_as_ram_setup:
pushl %ebx /* init detected */ pushl %edx /* bist */ - call cache_as_ram_main + call main
/* Should never see this postcode */ post_code(0xaf) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index dd02f6c..464f467 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -413,7 +413,7 @@ CAR_FAM10_ap_out: movl %esp, %ebp pushl %ebx /* Init detected. */ pushl %eax /* BIST */ - call cache_as_ram_main + call main
/* We will not go back. */
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index a001c93..ffa11ec 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,7 +1,6 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void done_cache_as_ram_main(void); void post_cache_as_ram(void);
diff --git a/src/include/cpu/intel/car.h b/src/include/cpu/intel/car.h deleted file mode 100644 index dc89ffc..0000000 --- a/src/include/cpu/intel/car.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _CPU_INTEL_CAR_H -#define _CPU_INTEL_CAR_H - -/* std signature of entry-point to romstage.c */ -void main(unsigned long bist); - -#endif /* _CPU_INTEL_CAR_H */ diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 9bc0ebc..1c066ac 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -24,6 +24,8 @@ void *memalign(size_t boundary, size_t size); void *malloc(size_t size); /* We never free memory */ static inline void free(void *ptr) {} +#else +void main(unsigned int arg1, unsigned int arg2); #endif
#endif /* STDLIB_H */ diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 3c3f9eb..1605360 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -41,10 +41,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index a153730..854e0ab 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -40,10 +40,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 7f78dce..c5d7a5e 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -53,10 +53,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index a17e68f..6cd5734 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -42,10 +42,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 20cb703..6ccf602 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -72,8 +72,10 @@ static int spd_read_byte(u32 device, u32 address) #include "spd.h" #include <reset.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index 51a713c..71ca437 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -29,10 +29,9 @@ #include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index e6646f5..3621b25 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -67,8 +67,10 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index f645812..f535056 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -48,10 +48,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index c9a04f5..a6f337a 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -60,8 +60,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..b06c031 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -40,8 +40,10 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 468f896..98d06ea 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -41,8 +41,10 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* all cores: allow caching of flash chip code and data diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 00223ae..d6eb10c 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -61,8 +61,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 13470e2..5e90301 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -70,8 +70,10 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 2daef93..737a682 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -44,10 +44,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 326a41a..0a3b400 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -39,8 +39,10 @@ #include "cbmem.h"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 7c143f4..91008d6 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -39,8 +39,10 @@ #include "cbmem.h"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val; AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5d530b7..1ea4f83 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -47,8 +47,10 @@
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index af4253d..329157d 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -56,8 +56,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 9158aad..f8aee36 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -30,10 +30,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/geode_gx2/cpureginit.c" #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl [] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index ec0682a..993a202 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -66,8 +66,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define RC2 ((1<<2)<<8) #define RC3 ((1<<3)<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 6388b42..5a2f7d1 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -182,8 +182,10 @@ static const u8 spd_addr[] = { #endif };
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 98a042a..08560b0 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -42,8 +42,10 @@
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 8ee42bd..a5dd8da 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -42,8 +42,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val; u8 byte; device_t dev; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index f5ac2e0..80df28e 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -70,8 +70,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 7ed520a..45562ee 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -40,8 +40,10 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
post_code(0x35); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 168b57f..9a430a6 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -40,8 +40,10 @@
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 7ef8a47..639176b 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -38,10 +38,9 @@ int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 3c7eb58..e84d848 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -61,8 +61,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 23e537f..4eb3023 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -56,10 +56,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
msr_t msr; static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index c7f3090..7ac4b9c 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -29,10 +29,9 @@ #include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index 6c18d8f..0d171ce 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 417f9a7..f4c4953 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -125,8 +125,10 @@ static void sio_init(void) pnp_exit_ext_func_mode(GPIO2345_DEV); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 5223360..2c541a0 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -42,8 +42,10 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 37f14f6..9dbf894 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -43,8 +43,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val, t32; u32 *addr32;
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index c0fa6a5..42cc087 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -80,8 +80,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..c86901a 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -139,8 +139,10 @@ static void sio_init(void) pnp_exit_ext_func_mode(GPIO_DEV); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..cd8483c 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -139,8 +139,10 @@ static void sio_init(void) pnp_exit_ext_func_mode(GPIO_DEV); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index 6db0866..8124bca 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -109,10 +109,9 @@ int mainboard_set_fbd_clock(int speed) return -1; } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) enable_lapic();
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index bdf03a7..b4240c7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -63,8 +63,10 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val; u8 byte; device_t dev; diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..2095ce9 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -95,8 +95,10 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM1, DIMM2, 0, diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index d12b77c..e7a2d03 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -85,8 +85,10 @@ static void sio_setup(void) pci_write_config32(dev, 0xa0, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */ DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */ diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..8f507a5 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -114,8 +114,10 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..27f35bc 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -211,8 +211,10 @@ static void m2v_bus_init(void) pci_write_config8(dev, 0xf0, 0x2e); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 0a03d59..29ec089 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -71,8 +71,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 84d2b97..745d0f2 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -71,8 +71,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 4753bb0..b5b8a64 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -71,8 +71,10 @@ static int spd_read_byte(u32 device, u32 address) #include <reset.h>
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 9ea6c04..4ad4026 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -33,10 +33,9 @@ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 87f8d65..bfe92a1 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -33,10 +33,9 @@ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 4faae20..32c04c8 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -40,10 +40,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 070b002..4f59f40 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -40,10 +40,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 64b4dae..ef60026 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -42,10 +42,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 8cf2b42..1992be4 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -41,10 +41,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 3c3f9eb..1605360 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -41,10 +41,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 825457e..617fcb6 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -73,10 +73,9 @@ static void disable_spd(void) { outb(0x67, PM_IO_BASE + 0x37); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 65f499b..bc86a1c 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -73,8 +73,10 @@ static int spd_read_byte(u32 device, u32 address) #include "spd.h" #include <reset.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index e733003..71fe231 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index 7325618..2266b8c 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -42,10 +42,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 41a65dd..1a4d28b 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -45,10 +45,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0}} }; diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index e733003..71fe231 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 3676a6d..533bcf9 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -80,10 +80,9 @@ static const struct mem_controller ctrl = { .d1f0 = 0x8000, .channel0 = { DIMM0 }, }; - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c index dd2553e..5c29304 100644 --- a/src/mainboard/bifferos/bifferboard/romstage.c +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -27,8 +27,7 @@ #include <console/console.h> #include <cpu/x86/cache.h>
-static void main(void) -{ +void main(unsigned int arg1, unsigned int arg2) { uint32_t tmp; post_code(0x05);
diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 43158bd..bfb996e 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -39,10 +39,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 03cdc1d..3cc2f03 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -49,8 +49,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define RC0 (6<<8) #define RC1 (7<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 8de8a83..398e958 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -41,10 +41,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* FIXME: Should be PC97307! */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 6a32c56..b9c91c2 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -68,7 +68,7 @@ static enum cb_err cubieboard_setup_power(void) return CB_SUCCESS; }
-void main(void) +void main(unsigned int arg1, unsigned int arg2) { void *entry; enum cb_err err; diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 0ae7610..4c3921d 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -25,10 +25,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) { #if 0 enable_lapic(); diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index b6412e8..782c384 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -153,10 +153,9 @@ static inline void irqinit(void){ *cp = 0xe; #endif } - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; volatile int i; for(i = 0; i < 100; i++) ; diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 6075565..2761516 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -29,10 +29,9 @@ int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl [] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index 040b937..ed4b866 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -299,10 +299,9 @@ static void enable_l2_cache(void) reg_nb_f1_e8 |= 3; pci_write_config8(NB1, 0xe8, reg_nb_f1_e8); } - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; device_t dev; u32 dmp_id;
diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index cbfe04d..8b5b462 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -11,10 +11,9 @@ #include "northbridge/amd/gx1/raminit.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 7deb730..8aec6da 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -36,10 +36,9 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c index 00dfecd..60aa3a7 100644 --- a/src/mainboard/emulation/qemu-armv7/romstage.c +++ b/src/mainboard/emulation/qemu-armv7/romstage.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <arch/stages.h>
-void main(void) +void main(unsigned int arg1, unsigned int arg2) { void *entry;
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 8dc61b2..cfe356a 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -32,10 +32,9 @@ #include "cpu/x86/lapic.h"
#include "memory.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int cbmem_was_initted;
/* init_timer(); */ diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 635a44f..468cf5b 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -33,10 +33,9 @@ #include "cpu/x86/lapic.h"
#include "../qemu-i440fx/memory.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int cbmem_was_initted;
/* init_timer(); */ diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 5ebc451..4bfb82a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -264,10 +264,9 @@ static void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0; int cbmem_was_initted; diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index d28ac34..ea4f555 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -39,10 +39,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index cad3694..7d63d96 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -39,10 +39,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; it8671f_48mhz_clkin(); it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 10bbb6f..69ac231 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -101,8 +101,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b2e1d70..4731358 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -92,8 +92,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index a0f9e76..7797847 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -67,8 +67,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index a0f9e76..7797847 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -67,8 +67,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index b9d27f7..8740f13 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -71,8 +71,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index b4af6d4..1e6528c 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -47,8 +47,10 @@ #define MSR_PSTATE_CONTROL 0xC0010062
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val; msr_t msr;
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 1c7b8ba..ce09d35 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -111,10 +111,9 @@ static void rcba_config(void) reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 25c6529..9797436 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -149,10 +149,9 @@ static void copy_spd(struct pei_data *peid) spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index a4daae5..c1f8b6e 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -112,10 +112,9 @@ static void rcba_config(void) reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 7967a55..923fe3d 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -224,7 +224,7 @@ static void simple_spi_test(void) #define simple_spi_test() #endif
-void main(void) +void main(unsigned int arg1, unsigned int arg2) {
extern struct mem_timings mem_timings; diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 44074c5..af6110e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -139,7 +139,7 @@ static struct mem_timings *setup_clock(void) return mem; }
-void main(void) +void main(unsigned int arg1, unsigned int arg2) { struct mem_timings *mem; void *entry; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 008f1f8..25c1ca8 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -153,10 +153,9 @@ static void early_ec_init(void) ec_write_cmd(EC_CMD_WARM_RESET); } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 2b42e73..a8c7b8b 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -94,8 +94,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define RC0 ((1<<1)<<8) #define RC1 ((1<<2)<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9deaaba..dffd4a6 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -115,8 +115,10 @@ static void setup_early_ipmi_serial() } #endif
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 474190b..eec7a3e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -91,8 +91,10 @@ static const u8 spd_addr[] = { #endif };
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index 85660c0..06e319a 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -36,10 +36,9 @@
/* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* TODO: It's a PC87364 actually! */ pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index ea848b4..27c881b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -36,8 +36,10 @@ #include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val; AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index eec574d..51ddb98 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -222,10 +222,9 @@ static void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0; int cbmem_was_initted; diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index b44668a..789cbdc 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -58,8 +58,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index c703b7a..c3d190e 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -58,8 +58,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index b8daac4..11c2874 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -31,10 +31,9 @@ #include "northbridge/amd/gx1/raminit.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index e1230e5..b87b1ba 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -70,8 +70,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 9a89107..2051dcf 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -31,10 +31,9 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
#include "northbridge/amd/gx1/raminit.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 2af0b2f..24a0e43 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -48,10 +48,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index d2e331e..1094049 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -52,10 +52,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include <cpu/amd/geode_lx/cpureginit.c> #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index 947b52d..d358394 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -52,10 +52,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include <cpu/amd/geode_lx/cpureginit.c> #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index cc956a7..8b8111e 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -173,8 +173,9 @@ static void rcba_config(void) RCBA32(FD) = reg32; }
-void main(FSP_INFO_HEADER *fsp_info_header) +void main(unsigned int arg1, unsigned int arg2) { +FSP_INFO_HEADER *fsp_info_header = (FSP_INFO_HEADER *)arg1; #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) int boot_mode = 0; #endif diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 982060c..d023625 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -34,10 +34,9 @@ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 94b6610..25a95b0 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -155,10 +155,9 @@ static void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0; int cbmem_was_initted; diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 99445b8..576f44b 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -119,10 +119,9 @@ static void early_config(void) /* Setup sata mode */ pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* int boot_mode = 0; */
static const struct mem_controller mch[] = { diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 12abb54..e182b8e 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -161,10 +161,9 @@ static void setup_sio_gpios(void) /* Turn off configuration mode. */ outb(0xaa, port); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index a672afa..bcc8a40 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -37,10 +37,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "debug.c" #include "arch/x86/lib/stages.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller mch[] = { { .node_id = 0, diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 2e99be5..b4df7bb 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -50,10 +50,9 @@ static inline int spd_read_byte(u16 device, u8 address) #if 0 /* skip_romstage doesn't compile with gcc */ #include "arch/x86/lib/stages.c" #endif - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; msr_t msr; u16 perf; static const struct mem_controller mch[] = { diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index c56b1df..640c319 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -50,10 +50,9 @@ static inline int spd_read_byte(u16 device, u8 address) #include "arch/x86/lib/stages.c"
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; msr_t msr; u16 perf; static const struct mem_controller mch[] = { diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index f35f93b..057661e 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -31,11 +31,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7501/raminit.c" #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" - -// This function MUST appear last (ROMCC limitation) -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 5ede2f9..db4f14c 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -331,10 +331,9 @@ static void poulsbo_setup_Stage2Regs(void) /* FIXME: CPU ID identification */ printk(BIOS_DEBUG, " done.\n"); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0;
if (bist == 0) diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index a429568..4e03ffa 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -65,8 +65,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index d2371b5..99bfdd3 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -65,8 +65,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 50869f7..b1a2534 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -65,8 +65,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index cc207b1..9407efe 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -85,10 +85,9 @@ static const struct mem_controller ctrl = { .d1f0 = 0x8000, .channel0 = { DIMM0 }, }; - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 7f91714..689408e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -63,8 +63,10 @@ */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 5121605..f3625b8 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -75,8 +75,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 842f7bc..3a6bb4b 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -328,10 +328,9 @@ static void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0; int cbmem_was_initted; diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 24cae41..f643e72 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -62,8 +62,10 @@ static inline int spd_read_byte(u32 device, u32 address)
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 98f5f10..abca2cf 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -158,10 +158,9 @@ static void superio_gpio_config(void) pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */ pnp_exit_ext_func_mode(dev); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 186e9fd..1575662 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -47,10 +47,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) { #if 0 enable_lapic(); diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index df46092..c200d98 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -107,10 +107,9 @@ static void rcba_config(void) RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index b2cd616..cd928c0 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -108,10 +108,9 @@ static void rcba_config(void) RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 01e48e7..d655c18 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -205,10 +205,9 @@ static void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0, dock_err; int cbmem_was_initted; diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 816fde4..f0828c3 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -70,8 +70,9 @@ static void early_lpc_setup(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); }
-void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; sysinfo_t sysinfo; int s3resume = 0; int cbmem_initted; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 5f8e291..c9b2099 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -214,10 +214,9 @@ static void set_fsb_frequency(void)
smbus_block_write(0x69, 0, 5, block); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1705003..b7dd584 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -147,10 +147,9 @@ init_usb (void) /* Relock registers. */ outw (0x0000, DEFAULT_PMBASE | 0x003c); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int s3resume = 0; u32 pm1_cnt; u16 pm1_sts; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 68a9b48..9d972c0 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -212,10 +212,9 @@ static void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0; int cbmem_was_initted; diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 61fd6bd..6b9ef33 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -46,8 +46,10 @@
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 3192e5c..241385a 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -70,10 +70,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_gx2/cpureginit.c" #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl [] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index b3b4498..773866f 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -109,10 +109,9 @@ static void mb_gpio_init(void) ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 2f7bd85..60856ce 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -151,10 +151,9 @@ static void mb_gpio_init(void) ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int err;
static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 18f48f6..64d1faf 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -84,10 +84,9 @@ static void mb_gpio_init(void) ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index c3f1c8a..0670da9 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -148,10 +148,9 @@ static void mb_gpio_init(void) ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int err;
static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index f9b9adf..65d3fd8 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -47,8 +47,10 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
/* diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index 59e1c6d..144e566 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -34,10 +34,9 @@ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init();
diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 578de61..62721c9 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -40,10 +40,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index a6767bc..7dbea8d 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -40,10 +40,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 3811cc5..e5ccf48 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -40,10 +40,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 4005ac8..bb35fbf 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -35,10 +35,9 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; w83627hf_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 15c02f5..7c7a911 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -105,8 +105,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, DIMM1, 0, 0, 0, 0, 0, 0, diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..63c0713 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -94,8 +94,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index aabc826..7c7cbe9 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -79,8 +79,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define RC0 (0x10<<8) #define RC1 (0x01<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 9a6e21f..9ac65cb 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -103,8 +103,10 @@ static void sio_setup(void) #define RC0 (2<<8) #define RC1 (1<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr[] = { // Node 0 RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..f80851d 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -99,8 +99,10 @@ static const u8 spd_addr[] = { #endif };
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; u8 reg; diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 97d0580..3efdaae 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -33,10 +33,9 @@ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index b34882e..0c41b42 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -65,8 +65,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 39c75ca..4dc76d6 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -39,10 +39,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c..b42e8d1 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -93,8 +93,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 93dd7c2..618c195 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -197,10 +197,9 @@ static inline u16 read_acpi16(u32 addr) { return inw(DEFAULT_PMBASE | addr); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 436edc0..3db7011 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -106,10 +106,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0}}, }; diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 9b272a4..b2dbed8 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -129,10 +129,9 @@ static void mb_gpio_init(void) outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */ outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */ } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0}}, }; diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 7dd4b48..6936d33 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -93,10 +93,9 @@ static void mb_early_setup(void) /* ACPI Enable */ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) { if (memory_initialized()) hard_reset(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index a4f55a8..c2403fe 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -250,10 +250,9 @@ static void init_artec_dongle(void) outb(0xf1, 0x88); outb(0xf4, 0x88); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 reg32; int boot_mode = 0; int cbmem_was_initted; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 0138936..d854261 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -119,10 +119,9 @@ static void default_superio_gpio_setup(void) outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; sysinfo_t sysinfo; int s3resume = 0; int cbmem_initted; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index f984af2..7f0649b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -131,10 +131,9 @@ static void early_pch_init(void) reg8 &= ~(1 << 2); pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 3abea10..50883e4 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -171,10 +171,9 @@ static void setup_sio_gpios(void) it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 3332999..03387b5 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -80,8 +80,10 @@ static inline int spd_read_byte(u32 device, u32 address) #define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) #define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index fccd29a..85aabb5 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -39,10 +39,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 7c112da..0f77fb0 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -89,8 +89,10 @@ static void sio_setup(void) lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index e3e7386..a4394d0 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -101,8 +101,10 @@ static void sio_setup(void) #define RC0 (2<<8) #define RC1 (1<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we don't know how to switch the SMBus to decode the CPU0 SPDs. So, The memory on each CPU must be an exact match. diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 7d1f834..042efff 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -89,8 +89,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index b393c34..3de54a8 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -100,8 +100,10 @@ static const u8 spd_addr[] = { #endif };
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 425f677..0cfb5d1 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -41,8 +41,10 @@ */ #define SIO_PORT 0x164e
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
post_code(0x30); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..897365e 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -165,8 +165,10 @@ static void write_GPIO(void) pnp_exit_ext_func_mode(GPIO3_DEV); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index da92d97..49b78e5 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -40,8 +40,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
post_code(0x30); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index fdf49d8..ed06e4f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -68,8 +68,10 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = { RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 6b10a68..2708c86 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -41,10 +41,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7525/raminit.c" #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller mch[] = { { .node_id = 0, diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 9a637be..22bf12c 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -45,10 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller mch[] = { { .node_id = 0, diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 09f4c57..fd69f1a 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -42,10 +42,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller mch[] = { { .node_id = 0, diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 3e51b73..b6c1e9b 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -44,10 +44,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller mch[] = { { .node_id = 0, diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 868fbdc..e71c896 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -44,10 +44,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller mch[] = { { .node_id = 0, diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index a52193f..b5129de 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -110,10 +110,9 @@ int mainboard_set_fbd_clock(int speed) return -1; } } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) enable_lapic();
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 68373b9..8b3487a 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -63,8 +63,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "speaker.c" #include "northbridge/amd/amdk8/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 0ba0fce..306294c 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -61,8 +61,10 @@ static inline int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 64de0c0..03953fe 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -135,10 +135,9 @@ static void hard_reset(void) print_err("Hard reset called.\n"); while (1) ; } - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; volatile int i; unsigned val;
diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index e733003..71fe231 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/amd/cs5530/enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index ed87462..e46f6a5 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -91,10 +91,9 @@ static void mb_early_setup(void) /* ACPI Enable */ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) { if (memory_initialized()) hard_reset(); diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c index 5dce23d..c4898be 100644 --- a/src/mainboard/ti/beaglebone/romstage.c +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -25,7 +25,7 @@ #include <arch/stages.h> #include <console/console.h>
-void main(void) +void main(unsigned int arg1, unsigned int arg2) { void *entry;
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 115b402..e7e72df 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -45,10 +45,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 78313fc..27ea5c4 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -39,10 +39,9 @@ int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 1b03982..a9a354b 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -33,10 +33,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7501/raminit.c" #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 952b19d..b96627d 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -55,8 +55,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 8f87257..ce85c70 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -55,8 +55,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 873652b..089ece3 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -55,8 +55,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index c020f3e..174946b 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -54,8 +54,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 873652b..089ece3 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -55,8 +55,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index df602ea..758ca31 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -54,8 +54,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index e97b026..743b1f5 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -68,8 +68,10 @@ static void sio_setup(void) #endif }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 57da072..a6b4a1c 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -63,8 +63,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 4f0e552..d0589f6 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -92,8 +92,10 @@ static void sio_setup(void) lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 55cb95e..7e738f2 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -94,8 +94,10 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 6dae693..f73726a 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -104,8 +104,10 @@ static const u8 spd_addr[] = { #endif };
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; struct sys_info *sysinfo = &sysinfo_car;
u32 bsp_apicid = 0, val, wants_reset; diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index c106b1c..b2af689 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -67,8 +67,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define RC2 ((1<<4)<<8) #define RC3 ((1<<3)<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const struct mem_controller cpu[] = { { .node_id = 0, diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 17379b5..ce961a6 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -71,8 +71,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define RC2 ((1<<4)<<8) #define RC3 ((1<<3)<<8)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index dc3bde2..873f51c 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -39,8 +39,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; u32 val;
post_code(0x30); diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index e7e65f2..7af870c 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -78,10 +78,9 @@ static const struct mem_controller ctrl = { .d1f0 = 0x8000, .channel0 = { DIMM0 }, }; - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index b3b515d..cad2b60 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -65,10 +65,9 @@ static void enable_shadow_ram(void) shadowreg |= 0x30; pci_write_config8(dev, 0x63, shadowreg); } - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; device_t dev;
/* Enable VGA; 32MB buffer. */ diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index c33acbe..da99e90 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -371,11 +371,9 @@ static void EmbedComInit(void) /* while(1); */ } #endif - -/* cache_as_ram.inc jumps to here. */ -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u16 boot_mode; u8 rambits, Data8, Data; device_t device; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 969e2b6..d5240b5 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -40,11 +40,9 @@ #include <superio/fintek/f81865f/f81865f.h>
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -/* cache_as_ram.inc jumps to here. */ -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; u32 tolm;
timestamp_init(rdtsc()); diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 5c1477d..62f1a37 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -100,10 +100,9 @@ static void enable_shadow_ram(void) shadowreg |= 0x30; pci_write_config8(ctrl.d0f3, 0x82, shadowreg); } - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; unsigned long x; device_t dev;
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index e839541..dee5b49 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -68,10 +68,9 @@ static void enable_shadow_ram(void) shadowreg |= 0x30; pci_write_config8(dev, 0x63, shadowreg); } - -#include <cpu/intel/car.h> -static void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; if (bist == 0) early_mtrr_init();
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index aa7e2de..9c5a18d 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -54,10 +54,9 @@ static const struct mem_controller ctrl = { .d1f0 = 0x8000, .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index d3ad0e2..13f9337 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -82,10 +82,9 @@ static void enable_shadow_ram(const struct mem_controller *ctrl) shadowreg |= 0x30; pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; /* Set statically so it should work with cx700 as well */ static const struct mem_controller cx700[] = { { diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index a725beb..8c26bd0 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -62,8 +62,10 @@ static void sio_setup(void)
}
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; + unsigned long cpu_init_detectedx = arg2; static const uint16_t spd_addr [] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index f9b4eec..c40e46e 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -50,10 +50,9 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1;
static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 07216d5..1ff57b3 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -48,10 +48,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_gx2/cpureginit.c" #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" - -#include <cpu/intel/car.h> -void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; static const struct mem_controller memctrl [] = { {.channel0 = {DIMM0, DIMM1}} }; diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index 3f9c70f..fe902d0 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -604,7 +604,7 @@ void init_VIA_chipset(void) * In the dev_enumerate() phase, */
-void main(void) +void main(unsigned int arg1, unsigned int arg2) { struct lb_memory *lb_mem; #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 2ab3e64..c32c968 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -284,8 +284,9 @@ void EmbedComInit(void) //while(1); }
-void main(unsigned long bist) +void main(unsigned int arg1, unsigned int arg2) { + unsigned long bist = arg1; unsigned cpu_reset = 0; u16 boot_mode; u8 rambits; diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index a63156f..8eff9c5 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -109,8 +109,9 @@ static void baytrail_rtc_init(void) }
/* Entry from cache-as-ram.inc. */ -void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header) +void main(unsigned int arg1, unsigned int arg2) { + FSP_INFO_HEADER *fsp_info_header = (FSP_INFO_HEADER *)arg1; const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; uint32_t fd_mask = 0; diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fd8b3b2..bc27ae4 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -39,8 +39,9 @@ #include <cpu/x86/msr.h> #include "gpio.h"
-void main(FSP_INFO_HEADER *fsp_info_header) +void main(unsigned int arg1, unsigned int arg2) { + FSP_INFO_HEADER *fsp_info_header = (FSP_INFO_HEADER *)arg1; uint32_t fd_mask = 0; uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;