Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
PS11:
so i'd guess that it's not correct to use the identical mask pmc_enable_std_gpe and pmc_disable_std_gpe to enable/disable the GPE0 and GPE1
GPE1 itself has separate register (under PMC IO) and not attached to pmc_enable_std_gpe which is nothing but GPE0_STS_127_96.
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