[coreboot-gerrit] Change in coreboot[master]: Performance improvement by removing delays in cpucp init

[Ravi Kumar Bokka (Code Review)]

Ravi Kumar Bokka has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63085 )

Change subject: Performance improvement by removing delays in cpucp init
......................................................................

Performance improvement by removing delays in cpucp init

As cpucp prepare takes 300 msec moving to before ramstage

BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board

Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi  
---
M src/mainboard/google/herobrine/romstage.c
M src/soc/qualcomm/sc7280/cpucp_load_reset.c
2 files changed, 11 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63085/1

diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c
index 2ea78b8..3dcb167 100644
--- a/src/mainboard/google/herobrine/romstage.c
+++ b/src/mainboard/google/herobrine/romstage.c
@@ -5,6 +5,7 @@
 #include <soc/qclib_common.h>
 #include "board.h"
 #include <soc/shrm.h>
+#include <soc/cpucp.h>

static void prepare_usb(void)
 {
@@ -15,11 +16,21 @@
    reset_usb0();
 }

+void cpucp_prepare(void)
+{
+	/* allow NS access to EPSS memory*/
+	setbits32(&epss_top->access_override, 0x1);
+
+	/* Enable subsystem clock. Required for CPUCP PDMEM access*/
+	setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1);
+}
+
 void platform_romstage_main(void)
 {
    shrm_fw_load_reset();
    /* QCLib: DDR init & train */
    qclib_load_and_run();
+	cpucp_prepare();
    prepare_usb();
    /* This rail needs to be stable by the time we take the FPMCU out of
       reset in ramstage, so already turn it on here. This needs to happen
diff --git a/src/soc/qualcomm/sc7280/cpucp_load_reset.c b/src/soc/qualcomm/sc7280/cpucp_load_reset.c
index d754531..b95cc75 100644
--- a/src/soc/qualcomm/sc7280/cpucp_load_reset.c
+++ b/src/soc/qualcomm/sc7280/cpucp_load_reset.c
@@ -9,24 +9,13 @@
 #include <device/mmio.h>
 #include <timer.h>

-void cpucp_prepare(void)
-{
-	/* allow NS access to EPSS memory*/
-	setbits32(&epss_top->access_override, 0x1);

-	/* Enable subsystem clock. Required for CPUCP PDMEM access*/
-	setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1);
-	if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1)))
-		printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
-}

void cpucp_fw_load_reset(void)
 {
    struct prog cpucp_fw_prog =
    	PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");

-	cpucp_prepare();
-
    if (!selfload(&cpucp_fw_prog))
    	die("SOC image: CPUCP load failed");