[coreboot-gerrit] Change in ...coreboot[master]: soc/cavium/cn81xx: Enable RNG for DRAM init

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31567 )

Change subject: soc/cavium/cn81xx: Enable RNG for DRAM init
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c 
File src/soc/cavium/cn81xx/sdram.c:

https://review.coreboot.org/#/c/31567/2/src/soc/cavium/cn81xx/sdram.c@67 
PS2, Line 67: 	/* Read back after enable so we know it is done. */
> That's what the reference code does without further comments. […]

Sounds fun :(

Is it a small set of registesr or some known banks? I don't know the platform, are there any attributes to set "strong uncacheable memory" like x86 where memory writes cannot be combined or posted.

Do you know for sure PCI MMCONF space does not require reads after writes to sync things?