[coreboot-gerrit] Change in coreboot[master]: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44890 )

Change subject: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree
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mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree

BUG=b:149970243
BRANCH=zork

Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890
Reviewed-by: Aaron Durbin 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
1 file changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 4413857..1620643 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -180,6 +180,15 @@

register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"

+	# genral purpose PCIe clock output configuration
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
+	register "gpp_clk_config[2]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD
+	register "gpp_clk_config[5]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[6]" = "GPP_CLK_OFF"
+
    device cpu_cluster 0 on
    	device lapic 0 on end
    end