Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40756 )
Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config ......................................................................
soc/intel/cannonlake: Add DisableHeciRetry to config
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter christian.walter@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b74291e..d4d76cd 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -194,6 +194,7 @@
/* Heci related */ uint8_t Heci3Enabled; + uint8_t DisableHeciRetry;
/* Gfx related */ uint8_t IgdDvmt50PreAlloc; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 010d152c..7af90a7 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -128,6 +128,10 @@ config->sata_port[i].TxGen3DeEmph; } } +#if !CONFIG(SOC_INTEL_COMETLAKE) + if (config->DisableHeciRetry) + tconfig->DisableHeciRetry = config->DisableHeciRetry; +#endif }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)