Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74383 )
Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ......................................................................
soc/intel/cmd/block/cse: Add config option for storing fw version info
This patch adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature.
BUG=b:273661726 TEST=Able to build and boot google/marasov.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I1678387261050b4b88b43860e1b988b135e47a98 --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74383/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 33d703f..b84942e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,15 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write.
+config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + bool + default n + depends on DRIVERS_INTEL_ISH + help + This configuration option stores CSE FPT partitions' version in CBMEM memory. + This information can be used to identify the currently running firmware partition + version. + config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE