[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/pantherlake: Add memory, romstage and ramstage FSP setup

[Jérémy Compostella (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Kapil Porwal, Pranava Y N, Subrata Banik.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84443?usp=email )

Change subject: soc/intel/pantherlake: Add memory, romstage and ramstage FSP setup
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Patch Set 5:

(1 comment)

This change is ready for review.

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/84443/comment/b1db019a_96f28136?usp... :
PS2, Line 54: 	m_cfg->LMemBar = 0xd0000000;
            : 		m_cfg->GttMmAdr = 0xcf000000;
> Add entries in iomap. […]

Done