[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64

[Nico Huber (Code Review)]

Attention is currently required from: Furquan Shaikh, Paul Menzel, Meera Ravindranath, Subrata Banik, Nick Vaccaro, Ronak Kanabar, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 )

Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
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Patch Set 8:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/52730/comment/ec8acc10_45703ec5 
PS8, Line 15: #define DDR5_CHANNELS			CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
It seems this is the only place where DDR5_PHYSICAL_CH_WIDTH is used?
This is a very obscure way (common code macro + Kconfig + odd constant)
to define something to `2`. Do we expect any Alder Lake SKU to have
DATA_BUS_WIDTH != 128?