Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34771 )
Change subject: soc/mediatek: dsi: Refactor PHY timing calculation
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Patch Set 9: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34771/6/src/soc/mediatek/common/dsi...
File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/34771/6/src/soc/mediatek/common/dsi...
PS6, Line 100: timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 |
: phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24;
That's an interesting idea, but I think the intent was different. […]
Ack
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