[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add restore and enable GPIO PM

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41712 )

Change subject: soc/intel/common: Add restore and enable GPIO PM
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Patch Set 5:
> Patch Set 5:
> > Patch Set 5:
> > > Patch Set 5:
> > >
> > > This patch can work on dedede and deltaur but you need remove board level hook. @Tim, I try the latest and still works fine at my side. Could you help review this?
> >
> > Eric, we're hoping that we don't need to use the LPIT & the associated ACPI methods to enable/disable GPIO PM. We are working on a cr50 + coreboot solution that should fix it.
> >
> > Do you think you need this soon?
>
> SGTM, but how do you plan to deal with factory H1 version 0.22? Sometimes this will cause H1 failed then enter recovery mode.

So the plan is to:
1) Add a new function to cr50 which will makes its IRQ pulses >= 100us.
2) Check cr50 FW version:
  a) if cr50 FW < MAGIC_NEW_VERSION, then disable the s0ix substate that causes GPIO PM to kick in, this will mean GPIO will eat more power, but this should only be the first boot from the factory.
  b) if cr50 FW >= MAGIC_NEW_VERSION, we'll enable the long IRQ pulses, and leave the LPM mode in its lowest s0ix substate