Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56335 )
Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ......................................................................
cpu/intel: Add dedicated file to grow Intel CPUIDs
This patch removes all local `CPUID_` macros from SoC directories and creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC users are expected to add any new CPUID support into cpu_ids.h and include 'cpu/intel/cpu_ids.h' into respective files that look for `CPUID_` macro.
Note: CPUIDs for HSW, BDW and Quark are still inside the respective directory.
Change-Id: I6fcd9b94da3f3779917220ea32bd5824bc7f7b9c Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/skx/include/soc/cpu.h 5 files changed, 62 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/56335/1
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h new file mode 100644 index 0000000..7094f6c --- /dev/null +++ b/src/include/cpu/intel/cpu_ids.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef CPU_INTEL_CPU_IDS_H +#define CPU_INTEL_CPU_IDS_H + +/* Supported CPUIDs for different Intel CPU */ + +#define CPUID_DENVERTON_A0_A1 0x506f0 +#define CPUID_DENVERTON_B0 0x506f1 +#define CPUID_COOPERLAKE_SP_A0 0x5065a +#define CPUID_COOPERLAKE_SP_A1 0x5065b +#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 +#define CPUID_SKYLAKE_SP_B0 0x506f1 +#define CPUID_SKYLAKE_SP_4 0x50654 +#define CPUID_SKYLAKE_C0 0x406e2 +#define CPUID_SKYLAKE_D0 0x406e3 +#define CPUID_SKYLAKE_HQ0 0x506e1 +#define CPUID_SKYLAKE_HR0 0x506e3 +#define CPUID_KABYLAKE_G0 0x406e8 +#define CPUID_KABYLAKE_H0 0x806e9 +#define CPUID_KABYLAKE_Y0 0x806ea +#define CPUID_KABYLAKE_HA0 0x506e8 +#define CPUID_KABYLAKE_HB0 0x906e9 +#define CPUID_CANNONLAKE_A0 0x60660 +#define CPUID_CANNONLAKE_B0 0x60661 +#define CPUID_CANNONLAKE_C0 0x60662 +#define CPUID_CANNONLAKE_D0 0x60663 +#define CPUID_APOLLOLAKE_A0 0x506c8 +#define CPUID_APOLLOLAKE_B0 0x506c9 +#define CPUID_APOLLOLAKE_E0 0x506ca +#define CPUID_GLK_A0 0x706a0 +#define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 +#define CPUID_WHISKEYLAKE_V0 0x806ec +#define CPUID_WHISKEYLAKE_W0 0x806eb +#define CPUID_COFFEELAKE_U0 0x906ea +#define CPUID_COFFEELAKE_B0 0x906eb +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed +#define CPUID_ICELAKE_A0 0x706e0 +#define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE_A0 0x906c0 +#define CPUID_COMETLAKE_U_A0 0xa0660 +#define CPUID_COMETLAKE_U_K0_S0 0xa0661 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 +#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 +#define CPUID_TIGERLAKE_A0 0x806c0 +#define CPUID_TIGERLAKE_B0 0x806c1 +#define CPUID_ELKHARTLAKE_A0 0x90660 +#define CPUID_ELKHARTLAKE_B0 0x90661 +#define CPUID_ALDERLAKE_S_A0 0x90670 +#define CPUID_ALDERLAKE_A0 0x906a0 +#define CPUID_ALDERLAKE_A1 0x906a1 +#define CPUID_ALDERLAKE_A2 0x906a2 + +#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index dd2653b..8a413ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -3,51 +3,10 @@ #ifndef SOC_INTEL_COMMON_BLOCK_MP_INIT_H #define SOC_INTEL_COMMON_BLOCK_MP_INIT_H
+#include <cpu/intel/cpu_ids.h> #include <device/device.h>
/* Supported CPUIDs for different SOCs */ -#define CPUID_SKYLAKE_C0 0x406e2 -#define CPUID_SKYLAKE_D0 0x406e3 -#define CPUID_SKYLAKE_HQ0 0x506e1 -#define CPUID_SKYLAKE_HR0 0x506e3 -#define CPUID_KABYLAKE_G0 0x406e8 -#define CPUID_KABYLAKE_H0 0x806e9 -#define CPUID_KABYLAKE_Y0 0x806ea -#define CPUID_KABYLAKE_HA0 0x506e8 -#define CPUID_KABYLAKE_HB0 0x906e9 -#define CPUID_CANNONLAKE_A0 0x60660 -#define CPUID_CANNONLAKE_B0 0x60661 -#define CPUID_CANNONLAKE_C0 0x60662 -#define CPUID_CANNONLAKE_D0 0x60663 -#define CPUID_APOLLOLAKE_A0 0x506c8 -#define CPUID_APOLLOLAKE_B0 0x506c9 -#define CPUID_APOLLOLAKE_E0 0x506ca -#define CPUID_GLK_A0 0x706a0 -#define CPUID_GLK_B0 0x706a1 -#define CPUID_GLK_R0 0x706a8 -#define CPUID_WHISKEYLAKE_V0 0x806ec -#define CPUID_WHISKEYLAKE_W0 0x806eb -#define CPUID_COFFEELAKE_U0 0x906ea -#define CPUID_COFFEELAKE_B0 0x906eb -#define CPUID_COFFEELAKE_P0 0x906ec -#define CPUID_COFFEELAKE_R0 0x906ed -#define CPUID_ICELAKE_A0 0x706e0 -#define CPUID_ICELAKE_B0 0x706e1 -#define CPUID_JASPERLAKE_A0 0x906c0 -#define CPUID_COMETLAKE_U_A0 0xa0660 -#define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 -#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 -#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 -#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 -#define CPUID_TIGERLAKE_A0 0x806c0 -#define CPUID_TIGERLAKE_B0 0x806c1 -#define CPUID_ELKHARTLAKE_A0 0x90660 -#define CPUID_ELKHARTLAKE_B0 0x90661 -#define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_A0 0x906a0 -#define CPUID_ALDERLAKE_A1 0x906a1 -#define CPUID_ALDERLAKE_A2 0x906a2 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index 0f9d3ace..f4b0d3c 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -3,6 +3,8 @@ #ifndef _CPU_INTEL_DENVERTON_NS_H #define _CPU_INTEL_DENVERTON_NS_H
+#include <cpu/intel/cpu_ids.h> + int get_cpu_count(void);
#ifndef __ASSEMBLER__ @@ -14,10 +16,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__
-/* Denverton-NS CPUID */ -#define CPUID_DENVERTON_A0_A1 0x506f0 -#define CPUID_DENVERTON_B0 0x506f1 - #define MSR_CORE_THREAD_COUNT 0x35 #define CORE_BIT_MSK 0x1 #define MCH_BAR_CORE_EXISTS_MASK 0x7164 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 716fe29e..d00c27f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -4,11 +4,9 @@ #define _SOC_CPU_H
#include <device/device.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h>
-#define CPUID_COOPERLAKE_SP_A0 0x5065a -#define CPUID_COOPERLAKE_SP_A1 0x5065b - void cpx_init_cpus(struct device *dev);
#endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 433598b..ef712ab 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -4,13 +4,9 @@ #define _SOC_CPU_H_
#include <device/device.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h>
-/* SKXSP CPUID */ -#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 -#define CPUID_SKYLAKE_SP_B0 0x506f1 -#define CPUID_SKYLAKE_SP_4 0x50654 - /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100