Attention is currently required from: Patrick Rudolph. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56243 )
Change subject: include/cpu/x86/msr: introduce IA32_MC_*(x) macros ......................................................................
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly.
Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/x86/msr.h M src/security/intel/txt/common.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/common/block/cpu/cpulib.c 11 files changed, 22 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/56243/1
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 1bcbc34..76c8521 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -63,7 +63,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index c7fcb36..883bd59 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -62,7 +62,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 28c3e78..f945f80 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -60,7 +60,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 7266a2c..3c78c09 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -45,7 +45,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9fcb527..2d8bd15 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -528,14 +528,14 @@ /* Enable all error reporting */ msr.lo = msr.hi = ~0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_CTL + (i * 4), msr); + wrmsr(IA32_MC_CTL(i), msr);
msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); }
/* All CPUs including BSP will run the following function. */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index dd2aeef..abf8f61 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -81,7 +81,7 @@ msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < 7; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); }
static void model_2065x_init(struct device *cpu) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7a40644..bfe1fa5 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -309,7 +309,7 @@ msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); }
static void model_206ax_report(void) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index da1932c..dd969d7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -56,7 +56,9 @@ #define DCA_TYPE0_EN (1 << 0) #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 +#define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank)) #define IA32_MC0_STATUS 0x401 +#define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank)) #define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32)) @@ -75,7 +77,9 @@ #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define IA32_MC0_ADDR 0x402 +#define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank)) #define IA32_MC0_MISC 0x403 +#define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank)) #define IA32_VMX_BASIC_MSR 0x480 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 011e8cc..2b7d926 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -483,7 +483,7 @@ */ size_t max_mc_msr = mca_get_bank_count(); for (size_t i = 0; i < max_mc_msr; i++) { - msr = rdmsr(IA32_MC0_STATUS + 4 * i); + msr = rdmsr(IA32_MC_STATUS(i)); if (!(msr.hi & MCA_STATUS_HI_UC)) continue;
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 920ee7d..0773101 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -119,8 +119,7 @@ ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, - IA32_MC0_CTL + (mci->bank * 4), 4); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, @@ -152,13 +151,13 @@ printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, mca_bank_name[bank]);
- msr = rdmsr(IA32_MC0_STATUS + (bank * 4)); + msr = rdmsr(IA32_MC_STATUS(bank)); printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_ADDR + (bank * 4)); + msr = rdmsr(IA32_MC_ADDR(bank)); printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_MISC + (bank * 4)); + msr = rdmsr(IA32_MC_MISC(bank)); printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_CTL + (bank * 4)); + msr = rdmsr(IA32_MC_CTL(bank)); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(MC0_CTL_MASK + bank); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); @@ -177,7 +176,7 @@ continue;
mci.bank = i; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); + mci.sts = rdmsr(IA32_MC_STATUS(i)); if (mci.sts.hi || mci.sts.lo) { mca_print_error(i);
@@ -194,7 +193,7 @@
/* Zero all machine check error status registers */ for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); }
void check_mca(void) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 81e42ae..9e95b0f 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -348,9 +348,9 @@
for (i = 0; i < num_banks; i++) { /* Clear the machine check status */ - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Initialize machine checks */ - wrmsr(IA32_MC0_CTL + i * 4, + wrmsr(IA32_MC_CTL(i), (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } }