Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71658 )
Change subject: mb/google/nissa/var/xivu: Update DPTF parameters ......................................................................
mb/google/nissa/var/xivu: Update DPTF parameters
Follow thermal table from thermal team.
1. Enable TS3 thermal sensor. 2. Set TS3 passive policy to 63. 3. Set TS3 critical policy to 73. 4. Modify TSR2 passive policy to CPU.
BUG=b:263554342 TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7 Signed-off-by: Ian Feng ian_feng@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658 Reviewed-by: Reka Norman rekanorman@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-by: AlanKY Lee alanky_lee@compal.corp-partner.google.com Reviewed-by: Dtrain Hsu dtrain_hsu@compal.corp-partner.google.com Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 32 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, but someone else must approve Dtrain Hsu: Looks good to me, approved Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved AlanKY Lee: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index bfaa639..e98750c 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -145,7 +145,8 @@ ## sensor information register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" - register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[2].desc" = ""ChargerMB"" + register "options.tsr[3].desc" = ""ChargerSUB""
# TODO: below values are initial reference values only ## Passive Policy @@ -153,7 +154,8 @@ [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 77, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 78, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 78, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 63, 5000), }"
## Critical Policy @@ -161,6 +163,7 @@ [0] = DPTF_CRITICAL(TEMP_SENSOR_0, 87, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_1, 78, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 88, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_3, 73, SHUTDOWN), }"
register "controls.power_limits" = "{