HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16616
-gerrit
commit 849380899289b044ae2da9f0522a46f506d58aae Author: Elyes HAOUAS ehaouas@noos.fr Date: Fri Sep 16 20:49:38 2016 +0200
src/mainboard: Add space around operators
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/advansus/a785e-i/mainboard.c | 2 +- src/mainboard/advansus/a785e-i/romstage.c | 2 +- src/mainboard/amd/bimini_fam10/mainboard.c | 2 +- src/mainboard/amd/bimini_fam10/romstage.c | 2 +- src/mainboard/amd/dbm690t/fadt.c | 2 +- src/mainboard/amd/dbm690t/mainboard.c | 4 +-- src/mainboard/amd/dbm690t/romstage.c | 12 ++++----- src/mainboard/amd/dinar/fadt.c | 2 +- src/mainboard/amd/dinar/gpio.c | 6 ++--- src/mainboard/amd/dinar/gpio.h | 4 +-- src/mainboard/amd/dinar/mainboard.c | 2 +- src/mainboard/amd/inagua/BiosCallOuts.c | 2 +- src/mainboard/amd/inagua/broadcom.c | 22 ++++++++-------- src/mainboard/amd/mahogany/mainboard.c | 2 +- src/mainboard/amd/mahogany/romstage.c | 12 ++++----- src/mainboard/amd/mahogany_fam10/mainboard.c | 2 +- src/mainboard/amd/mahogany_fam10/romstage.c | 2 +- src/mainboard/amd/persimmon/BiosCallOuts.c | 2 +- src/mainboard/amd/pistachio/fadt.c | 2 +- src/mainboard/amd/pistachio/mainboard.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 12 ++++----- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 8 +++--- src/mainboard/amd/serengeti_cheetah/fadt.c | 8 +++--- src/mainboard/amd/serengeti_cheetah/mptable.c | 16 ++++++------ src/mainboard/amd/serengeti_cheetah/romstage.c | 14 +++++----- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 8 +++--- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 8 +++--- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 8 +++--- .../amd/serengeti_cheetah_fam10/mptable.c | 20 +++++++-------- .../amd/serengeti_cheetah_fam10/romstage.c | 10 ++++---- src/mainboard/amd/south_station/BiosCallOuts.c | 2 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 2 +- src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 2 +- src/mainboard/amd/torpedo/fadt.c | 2 +- src/mainboard/amd/torpedo/gpio.c | 6 ++--- src/mainboard/amd/torpedo/gpio.h | 4 +-- src/mainboard/amd/torpedo/mainboard.c | 2 +- src/mainboard/amd/union_station/BiosCallOuts.c | 2 +- src/mainboard/artecgroup/dbe61/romstage.c | 2 +- src/mainboard/asrock/939a785gmh/mainboard.c | 2 +- src/mainboard/asrock/939a785gmh/romstage.c | 12 ++++----- src/mainboard/asus/a8v-e_deluxe/romstage.c | 4 +-- src/mainboard/asus/a8v-e_se/romstage.c | 4 +-- src/mainboard/asus/kcma-d8/acpi_tables.c | 2 +- src/mainboard/asus/kcma-d8/mainboard.c | 2 +- src/mainboard/asus/kcma-d8/romstage.c | 10 ++++---- src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 4 +-- src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c | 4 +-- src/mainboard/asus/kgpe-d16/acpi_tables.c | 2 +- src/mainboard/asus/kgpe-d16/mainboard.c | 2 +- src/mainboard/asus/kgpe-d16/romstage.c | 10 ++++---- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 8 +++--- src/mainboard/asus/m4a78-em/mainboard.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/mainboard.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/asus/m5a88-v/mainboard.c | 2 +- src/mainboard/asus/m5a88-v/romstage.c | 2 +- src/mainboard/avalue/eax-785e/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 4 +-- src/mainboard/broadcom/blast/mptable.c | 20 +++++++-------- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 8 +++--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 4 +-- src/mainboard/gigabyte/m57sli/fanctl.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 14 +++++----- src/mainboard/gigabyte/m57sli/romstage.c | 4 +-- src/mainboard/gigabyte/ma785gm/mainboard.c | 2 +- src/mainboard/gigabyte/ma785gm/romstage.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 2 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +- src/mainboard/gigabyte/ma78gm/mainboard.c | 2 +- src/mainboard/gigabyte/ma78gm/romstage.c | 2 +- src/mainboard/google/butterfly/chromeos.c | 2 +- src/mainboard/google/butterfly/hda_verb.c | 12 ++++----- src/mainboard/google/butterfly/mainboard.c | 2 +- src/mainboard/google/cyan/spd/spd.c | 6 ++--- src/mainboard/google/falco/Makefile.inc | 16 ++++++------ src/mainboard/google/guado/lan.c | 2 +- src/mainboard/google/guado/romstage.c | 4 +-- src/mainboard/google/guado/smihandler.c | 8 +++--- src/mainboard/google/jecht/lan.c | 2 +- src/mainboard/google/link/i915io.c | 16 ++++++------ src/mainboard/google/ninja/lan.c | 2 +- src/mainboard/google/panther/lan.c | 2 +- src/mainboard/google/peach_pit/mainboard.c | 6 ++--- src/mainboard/google/rikku/lan.c | 2 +- src/mainboard/google/rikku/romstage.c | 4 +-- src/mainboard/google/rikku/smihandler.c | 8 +++--- src/mainboard/google/stout/mainboard.c | 2 +- src/mainboard/google/tidus/lan.c | 2 +- src/mainboard/google/tidus/led.c | 8 +++--- src/mainboard/hp/dl145_g1/acpi_tables.c | 4 +-- src/mainboard/hp/dl145_g1/fadt.c | 12 ++++----- src/mainboard/hp/dl145_g1/get_bus_conf.c | 4 +-- src/mainboard/hp/dl145_g1/romstage.c | 18 ++++++------- src/mainboard/hp/dl145_g3/get_bus_conf.c | 6 ++--- src/mainboard/hp/dl145_g3/mptable.c | 4 +-- src/mainboard/hp/dl145_g3/romstage.c | 12 ++++----- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 6 ++--- src/mainboard/hp/dl165_g6_fam10/mptable.c | 4 +-- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 16 ++++++------ src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- src/mainboard/intel/bayleybay_fsp/romstage.c | 2 +- src/mainboard/intel/eagleheights/debug.c | 6 ++--- src/mainboard/intel/minnowmax/gpio.c | 2 +- src/mainboard/intel/stargo2/gpio.h | 8 +++--- src/mainboard/intel/truxton/Makefile.inc | 2 +- src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/acpi_tables.c | 8 +++--- src/mainboard/iwill/dk8_htx/fadt.c | 8 +++--- src/mainboard/iwill/dk8_htx/mptable.c | 18 ++++++------- src/mainboard/iwill/dk8_htx/romstage.c | 4 +-- src/mainboard/jetway/j7f2/romstage.c | 4 +-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 2 +- src/mainboard/jetway/pa78vm5/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 30 +++++++++++----------- src/mainboard/kontron/kt690/fadt.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 +-- src/mainboard/kontron/kt690/romstage.c | 12 ++++----- src/mainboard/lenovo/t430s/hda_verb.c | 12 ++++----- src/mainboard/lenovo/t530/hda_verb.c | 12 ++++----- src/mainboard/lenovo/x230/hda_verb.c | 12 ++++----- src/mainboard/lippert/frontrunner-af/mainboard.c | 4 +-- src/mainboard/lippert/hurricane-lx/mainboard.c | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 4 +-- src/mainboard/lippert/literunner-lx/mainboard.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 6 ++--- src/mainboard/lippert/roadrunner-lx/mainboard.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 6 ++--- src/mainboard/lippert/spacerunner-lx/mainboard.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 6 ++--- src/mainboard/lippert/toucan-af/mainboard.c | 4 +-- src/mainboard/msi/ms9185/mptable.c | 20 +++++++-------- src/mainboard/msi/ms9185/romstage.c | 6 ++--- src/mainboard/msi/ms9282/mptable.c | 8 +++--- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 10 ++++---- src/mainboard/msi/ms9652_fam10/mptable.c | 8 +++--- src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 4 +-- src/mainboard/roda/rk886ex/m3885.c | 6 ++--- src/mainboard/roda/rk886ex/mainboard.c | 6 ++--- src/mainboard/roda/rk886ex/romstage.c | 2 +- src/mainboard/samsung/lumpy/gpio.c | 8 +++--- src/mainboard/samsung/stumpy/romstage.c | 4 +-- src/mainboard/samsung/stumpy/smihandler.c | 8 +++--- src/mainboard/siemens/mc_tcu3/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/fadt.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 12 ++++----- src/mainboard/sunw/ultra40/mptable.c | 16 ++++++------ src/mainboard/sunw/ultra40m2/romstage.c | 4 +-- src/mainboard/supermicro/h8dme/mptable.c | 10 ++++---- src/mainboard/supermicro/h8dmr/mptable.c | 10 ++++---- src/mainboard/supermicro/h8dmr/romstage.c | 4 +-- .../supermicro/h8dmr_fam10/get_bus_conf.c | 6 ++--- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 8 +++--- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/fadt.c | 2 +- .../supermicro/h8qme_fam10/get_bus_conf.c | 6 ++--- src/mainboard/supermicro/h8qme_fam10/mptable.c | 8 +++--- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8scm/fadt.c | 2 +- src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 2 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- src/mainboard/technexion/tim5690/fadt.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 12 ++++----- src/mainboard/technexion/tim5690/tn_post_code.c | 4 +-- src/mainboard/technexion/tim8690/fadt.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 4 +-- src/mainboard/technexion/tim8690/romstage.c | 12 ++++----- src/mainboard/thomson/ip1000/mainboard.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 6 ++--- src/mainboard/tyan/s2912/mptable.c | 8 +++--- src/mainboard/tyan/s2912/romstage.c | 4 +-- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 6 ++--- src/mainboard/tyan/s2912_fam10/mptable.c | 8 +++--- src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- src/mainboard/tyan/s8226/BiosCallOuts.c | 4 +-- src/mainboard/tyan/s8226/fadt.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 4 +-- src/mainboard/winent/mb6047/mptable.c | 4 +-- src/mainboard/winent/mb6047/romstage.c | 4 +-- 195 files changed, 533 insertions(+), 533 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index be37d2d..23e304d 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -67,7 +67,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard A785E-I Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); enable_int_gfx(); diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 55c94a6..45e5d50 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 3c6c2c6..59c1b8c 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -121,7 +121,7 @@ static void get_ide_dma66(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard BIMINI Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); enable_int_gfx(); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index be381a1..9ea7e44 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c index f9768b2..8888f98 100644 --- a/src/mainboard/amd/dbm690t/fadt.c +++ b/src/mainboard/amd/dbm690t/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 22170c0..5598386 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -71,7 +71,7 @@ static void enable_onboard_nic(void) /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */ byte = inb(0xC51); byte &= 0x3F; - byte |= 0x80; /* 7:6=10 */ + byte |= 0x80; /* 7:6 = 10 */ outb(byte, 0xC51);
/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */ @@ -178,7 +178,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard DBM690T Enable. dev = 0x%p\n", dev);
enable_onboard_nic(); get_ide_dma66(); diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 517f75b..440e5e6 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_dbm690t_resource_map();
@@ -109,16 +109,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } @@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c index 977a6ce..1aad0b5 100644 --- a/src/mainboard/amd/dinar/fadt.c +++ b/src/mainboard/amd/dinar/fadt.c @@ -54,7 +54,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index 17097b3..affda6f 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -179,7 +179,7 @@ gpioEarlyInit( RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
- // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -357,7 +357,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO - // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) + // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); // } @@ -377,7 +377,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO - // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) + // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h index c61f445..f53eb87 100644 --- a/src/mainboard/amd/dinar/gpio.h +++ b/src/mainboard/amd/dinar/gpio.h @@ -1750,7 +1750,7 @@
typedef enum _GPIO_COUNT { - GPIO_00=0, + GPIO_00 = 0, GPIO_01, GPIO_02, GPIO_03, @@ -2227,7 +2227,7 @@ GPIO_SETTINGS gpio_table[]=
typedef enum _GEVENT_COUNT { - GEVENT_00=0x60, + GEVENT_00 = 0x60, GEVENT_01, GEVENT_02, GEVENT_03, diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 947ec65..9f2e10a 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -66,7 +66,7 @@ void set_pcie_dereset(void *nbconfig) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard Dinar Enable. dev = 0x%p\n", dev); }
struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 3a45761..10022c3 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -138,7 +138,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 905f6c3..4de1c52 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -73,7 +73,7 @@ void broadcom_init(void); * programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and * won't say anything about their purpose. Appearently hardware designers are * expected to blindly copy the Inagua reference schematic: GBE_STAT2: - * 0=activity; GBE_STAT[1:0]: 11=no link, 10=10Mbit, 01=100Mbit, 00=1Gbit. + * 0 = activity; GBE_STAT[1:0]: 11 = no link, 10 = 10Mbit, 01 = 100Mbit, 00 = 1Gbit. * * For package processing the 5785 also features a MIPS-based RISC CPU, booting * from an internal ROM. The firmware loads config data and supplements (e.g. to @@ -119,7 +119,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! u16 basic_config; //?, see below u8 checksum; //byte sum of header == 0 u8 unknown2; //?, patch rejected if changed - u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1=a, 2=b, ...) + u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...) } header;
struct { /* Init code */ @@ -197,8 +197,8 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! /* Bitfield enabling general features/codepaths in the firmware or * selecting support for one of several supported PHYs? * Bits not listed had no appearent effect: - * 14-11: any bit 1=firmware execution seemed delayed - * 10: 0=firmware execution seemed delayed + * 14-11: any bit 1 = firmware execution seemed delayed + * 10: 0 = firmware execution seemed delayed * 9,2,0: select PHY type, affects these registers, probably more * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes * -------+---------------------------------------------------------- @@ -221,7 +221,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * never seen used. Generally, lower values appear to be run earlier. * An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60, * 68, 20, 70, 80 to be interpreted in this order. - * All tests were performed with .basic_config=0x0604. + * All tests were performed with .basic_config = 0x0604. */ .init.hunk1_when = 0x10, //only once at RISC CPU reset? /* Instructions are obviously a specialized bytecode interpreted by the @@ -250,7 +250,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) #endif - be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12=1: auto-clock-switch + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars be(0x06100D38), be(0x00000000), //v1.03 : - | be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| @@ -287,7 +287,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0x08380000), //CFR-AF: PHY18| be(0x083C0000), //CFR-AF: PHY1C| #endif - be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0==1 -->skip next 12 bytes + be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode #else @@ -304,9 +304,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY #endif be(0xF7F30116), // IDDQ PHY - be(0xC40005A0), //v1.09 : 5A0.0=0: Port Mode = MII - be(0xC4180400), //v1.09 : 400.3=0| - be(0xC3100400), //v1.09 : 400.2=1| + be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII + be(0xC4180400), //v1.09 : 400.3 = 0| + be(0xC3100400), //v1.09 : 400.2 = 1| }, //-->PWRDN_LENGTH!
}; @@ -326,7 +326,7 @@ void broadcom_init(void) printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow);
/* Halt RISC CPU before uploading the firmware patch */ - for (i=10000; i > 0; i--) { + for (i = 10000; i > 0; i--) { gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state gec_base[0x5000/4] |= (1<<10); //issue RISC halt if (gec_base[0x5000/4] | (1<<10)) diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 9bf3a67..0f52e29 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -95,7 +95,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 662e7cf..547e9a4 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_mahogany_resource_map();
@@ -110,16 +110,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } @@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs780_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 8c244d4..9d4845c 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -96,7 +96,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 3428aab..1ee6698 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 9a2a9bb..f341014 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -63,7 +63,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c index f9768b2..8888f98 100644 --- a/src/mainboard/amd/pistachio/fadt.c +++ b/src/mainboard/amd/pistachio/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 6efd700..1db65fb 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -248,7 +248,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard Pistachio Enable. dev = 0x%p\n", dev);
enable_onboard_nic(); set_thermal_config(); diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index c78f0d2..d6dd0d2 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -84,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_pistachio_resource_map();
@@ -112,16 +112,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } @@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
post_code(0x06);
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index f75f820..ddc232f 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -37,7 +37,7 @@
unsigned long acpi_fill_madt(unsigned long current) { - u32 gsi_base=0x18; + u32 gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -149,11 +149,11 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; - if(i<7) { + if(i < 7) { c = (u8) ('4' + i - 1); } else { diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index bd00961..6bb03e9 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -37,13 +37,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x03; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 8236e7b..042b030 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) { @@ -104,31 +104,31 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 }
//Slot 4 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 }
//Slot 1 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // }
//Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 }
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; device_t dev; @@ -141,7 +141,7 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { + for(ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // } } @@ -152,7 +152,7 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { + for(ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 } } diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 51fce31..1671d9a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -38,7 +38,7 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
@@ -49,11 +49,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0); } @@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { /* Read FIDVID_STATUS */ msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); }
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); }
@@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0 int i; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { activate_spd_rom(&cpu[i]); dump_smbus_registers(); } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 7496a60..f2f6bc4 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -29,7 +29,7 @@
unsigned long acpi_fill_madt(unsigned long current) { - u32 gsi_base=0x18; + u32 gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { u32 d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -138,11 +138,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, /* same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table */
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; - if(i<7) { + if(i < 7) { c = (u8) ('4' + i - 1); } else { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 3183a7e..7f54896 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -40,13 +40,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x03; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 66dee18..87ca672 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -103,7 +103,7 @@ void get_bus_conf(void) m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -141,8 +141,8 @@ void get_bus_conf(void) }
/* HT chain 1 */ - j=0; - for(i=1; i< sysconf.hc_possible_num; i++) { + j = 0; + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue;
// check hcid type here @@ -199,7 +199,7 @@ void get_bus_conf(void) m->apicid_8111 = apicid_base + 0; m->apicid_8132_1 = apicid_base + 1; m->apicid_8132_2 = apicid_base + 2; - for(i=0;i<j;i++) { + for(i = 0; i < j; i++) { m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 7b2e22e..b71df58 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) { @@ -106,31 +106,31 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 }
// Slot 4 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 }
// Slot 1 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // }
//Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 }
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; int jj; @@ -143,9 +143,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - for(jj=0; jj<4; jj++) { + for(jj = 0; jj < 4; jj++) { //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { + for(ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); // } } @@ -156,9 +156,9 @@ static void *smp_write_config_table(void *v) if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - for(jj=0; jj<4; jj++) { + for(jj = 0; jj < 4; jj++) { //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { + for(ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25 } } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 0c84b6d..d00bfbc 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -51,7 +51,7 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
@@ -63,11 +63,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);
- /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7))); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); smbus_write_byte(SMBUS_HUB, 0x03, 0); }
@@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index e68db13..7f28eb9 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -138,7 +138,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 6652723..bffbe60 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -271,7 +271,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 68281e7..1faac4d 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 6f5e0a9..2e370bf 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -108,7 +108,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index fba8fc8..b20cfc8 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index b9fe745..ac98557 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -177,7 +177,7 @@ gpioEarlyInit( RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
- // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW) RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); @@ -355,7 +355,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO -// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) +// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable) // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); // } @@ -375,7 +375,7 @@ gpioEarlyInit( } // else // { // 0 - AUTO -// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) +// // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH) // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index f5decb3..0f78b83 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -1750,7 +1750,7 @@
typedef enum _GPIO_COUNT { - GPIO_00=0, + GPIO_00 = 0, GPIO_01, GPIO_02, GPIO_03, @@ -2227,7 +2227,7 @@ const GPIO_SETTINGS gpio_table[]=
typedef enum _GEVENT_COUNT { - GEVENT_00=0x60, + GEVENT_00 = 0x60, GEVENT_01, GEVENT_02, GEVENT_03, diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index d90cb84..9bae0bf 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -49,7 +49,7 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev = 0x%p\n", dev); }
struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index e68db13..7f28eb9 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -138,7 +138,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi // Get SB800 MMIO Base (AcpiMmioAddr) WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index c8bd9cc..b0bfc5b 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -36,7 +36,7 @@ int spd_read_byte(unsigned int device, unsigned int address) int i;
if (device == DIMM0) { - for (i=0; i < (ARRAY_SIZE(spd_table)); i++) { + for (i = 0; i < (ARRAY_SIZE(spd_table)); i++) { if (spd_table[i].address == address) { return spd_table[i].data; } diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 169e6c6..cbfa421 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -93,7 +93,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index b4023e0..567a21d 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_939a785gmh_resource_map();
@@ -175,16 +175,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } @@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs780_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index e6b8ef5..b8f631b 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -126,8 +126,8 @@ static void sio_init(void) pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_exit_ext_func_mode(GPIO_DEV); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4a33f77..4c74d0f 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -126,8 +126,8 @@ static void sio_init(void) pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_exit_ext_func_mode(GPIO_DEV); diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c index 8395b9d..8af85f9 100644 --- a/src/mainboard/asus/kcma-d8/acpi_tables.c +++ b/src/mainboard/asus/kcma-d8/acpi_tables.c @@ -30,7 +30,7 @@ unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; - u32 gsi_base=0; + u32 gsi_base = 0; uint32_t apicid_sp5100; uint32_t apicid_sr5650; /* create all subtables for processors */ diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c index 0219ee6..eddf942 100644 --- a/src/mainboard/asus/kcma-d8/mainboard.c +++ b/src/mainboard/asus/kcma-d8/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard KCMA-D8 initializing, dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard KCMA-D8 initializing, dev = 0x%p\n", dev);
msr_t msr, msr2;
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index e06e02b..256cf7e 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -256,7 +256,7 @@ static void execute_memory_test(void) uint32_t readback; uint32_t start = 0x300000; printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); *dataptr = 0x55555555; dataptr = (void *)(start + i + 4); @@ -264,7 +264,7 @@ static void execute_memory_test(void) } printk(BIOS_DEBUG, "Done!\n"); printk(BIOS_DEBUG, "Testing memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); readback = *dataptr; if (readback != 0x55555555) @@ -281,7 +281,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -301,7 +301,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -499,7 +499,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); }
diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c index 435731d..1a9931f 100644 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -118,11 +118,11 @@ void get_bus_conf(void)
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } else { apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base); } apicid_ck804 = apicid_base + 0; } diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0889f24..c7fa429 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); }
diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c index 101997a..9177477 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c @@ -107,10 +107,10 @@ void get_bus_conf(void)
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } else { apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base); } apicid_ck804 = apicid_base + 0; } diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 8395b9d..8af85f9 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -30,7 +30,7 @@ unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; - u32 gsi_base=0; + u32 gsi_base = 0; uint32_t apicid_sp5100; uint32_t apicid_sr5650; /* create all subtables for processors */ diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 65029d4..3d48053 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev = 0x%p\n", dev);
msr_t msr, msr2;
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index e5550bd..80d1c45 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -297,7 +297,7 @@ static void execute_memory_test(void) uint32_t readback; uint32_t start = 0x300000; printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); *dataptr = 0x55555555; dataptr = (void *)(start + i + 4); @@ -305,7 +305,7 @@ static void execute_memory_test(void) } printk(BIOS_DEBUG, "Done!\n"); printk(BIOS_DEBUG, "Testing memory...\n"); - for (i=0; i < 0x1000000; i = i + 8) { + for (i = 0; i < 0x1000000; i = i + 8) { dataptr = (void *)(start + i); readback = *dataptr; if (readback != 0x55555555) @@ -322,7 +322,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -342,7 +342,7 @@ static void execute_memory_test(void) x = 0xaaaaaaaa; y = 0x12345678; z = 0x87654321; - for (i=0; i < 0x1000000; i = i + 4) { + for (i = 0; i < 0x1000000; i = i + 4) { /* Use Xorshift as a PRNG to stress test the bus */ v = x; v ^= v << 11; @@ -540,7 +540,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); }
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 3bf54db..50e9f65 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); - printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%02x\n", bsp_apicid);
/* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 9eacecf..c61557b 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -154,10 +154,10 @@ static void m2v_it8712f_gpio_init(void) * pcirst5# -> maybe n/c (untested) * * For software control of PCIRST[1-5]#: - * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control) - * 0x25=0x17 (select gpio function) - * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable - * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable + * 0x2a = 0x17 (deselect pcirst# hardwiring, enable 0x25 control) + * 0x25 = 0x17 (select gpio function) + * 0xc0 = 0x17, 0xc8 = 0x17 gpio port 1 select & output enable + * 0xc4 = 0xc1, 0xcc = 0xc1 gpio port 5 select & output enable */ giv = gpio_init_data; while (giv->addr) { diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 64bd058..e4c5e0e 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -116,7 +116,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 844fc93..6c081d4 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 7c66257..875c017 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -188,7 +188,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index e43dbbc..2393e38 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 941ba26..67c0b5a 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -68,7 +68,7 @@ u8 is_dev3_present(void) static void mainboard_enable(device_t dev) {
- printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); enable_int_gfx(); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 1630497..28867ee 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index ff1aa9e..0dc2552 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 0a3ba72..5f6f29a 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -48,7 +48,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
- /* bit=0 means enable function (per CX700 datasheet) + /* bit = 0 means enable function (per CX700 datasheet) * 5 16.1 USB 2 * 4 16.0 USB 1 * 3 15.0 SATA and PATA @@ -57,7 +57,7 @@ static void enable_mainboard_devices(void) */ pci_write_config8(dev, 0x50, 0x80);
- /* bit=1 means enable internal function (per CX700 datasheet) + /* bit = 1 means enable internal function (per CX700 datasheet) * 3 Internal RTC * 2 Internal PS2 Mouse * 1 Internal KBC Configuration diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d283d85..f666f70 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) { device_t dev = 0; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
//USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i=0;i<3;i++) { + for(i = 0; i < 3; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // }
@@ -85,13 +85,13 @@ static void *smp_write_config_table(void *v) }
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // }
//pci slot (on bcm5785) - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // }
@@ -100,34 +100,34 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // }
- for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // }
//onboard Broadcom - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // }
// First PCI-E x8 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); // }
// Second PCI-E x8 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // }
// Third PCI-E x1 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); // }
diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index e801ae3..f7c4b2d 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -16,7 +16,7 @@ # http://www.arm.com/products/tools/development-boards/versatile-express
# To execute, do: -# export QEMU_AUDIO_DRV=none +# export QEMU_AUDIO_DRV = none # qemu-system-arm -M vexpress-a9 -m 1024M -nographic -bios build/coreboot.rom
if BOARD_EMULATION_QEMU_ARMV7 diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 46281ff..63b1833 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -33,7 +33,7 @@ static void qemu_nb_init(device_t dev) uint8_t v = pci_read_config8(dev, 0x59); v |= 0x30; pci_write_config8(dev, 0x59, v); - for (i=0; i<6; i++) + for (i = 0; i < 6; i++) pci_write_config8(dev, 0x5a + i, 0x33);
/* This sneaked in here, because Qemu does not diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 396a2ec..cc01095 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -126,7 +126,7 @@ static void early_superio_config(void) { device_t dev;
- dev=PNP_DEV(0x4e, 0x00); + dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev); pnp_write_register(dev, 0x02, 0x0e); // UART power diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 8a955e8..a7962f54 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) PCI_INT(0, sbdn+5, 2, 0x15); // 21 PCI_INT(0, sbdn+8, 0, 0x16); // 22
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!bus_sis966[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<2; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 2; j++) + for(i = 0; i < 4; i++) { PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 8bc71a9..6166851 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c index 07a2666..cc0cdca 100644 --- a/src/mainboard/gigabyte/m57sli/fanctl.c +++ b/src/mainboard/gigabyte/m57sli/fanctl.c @@ -75,7 +75,7 @@ static const struct { void init_ec(uint16_t base) { int i; - for (i=0; i<ARRAY_SIZE(sequence); i++) { + for (i = 0; i < ARRAY_SIZE(sequence); i++) { write_index(base, sequence[i].index, sequence[i].value); } } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index e6cb28b..403b969 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -84,9 +84,9 @@ static void *smp_write_config_table(void *v)
/* The PCIe slots, each on its own bus */ k = 1; - for(i=0; i<4; i++){ - for(j=7; j>1; j--){ - if(k>3) k=0; + for(i = 0; i < 4; i++){ + for(j = 7; j > 1; j--){ + if(k > 3) k = 0; PCI_INT(j,0,i, 16+k); k++; } @@ -97,10 +97,10 @@ static void *smp_write_config_table(void *v) physical PCI slots are j = 7,8 FireWire is j = 10 */ - k=2; - for(i=0; i<4; i++){ - for(j=6; j<11; j++){ - if(k>3) k=0; + k = 2; + for(i = 0; i < 4; i++){ + for(j = 6; j < 11; j++){ + if(k > 3) k = 0; PCI_INT(1,j,i, 16+k); k++; } diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b1c849b..a59e725 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index ac53c43..8a109db 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -132,7 +132,7 @@ static void set_gpio40_gfx(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index baf49af..06eaa8c 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 187c30e..9e42d5d 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -242,7 +242,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index b8ab282..860b1f1 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 505ba3e..9e214c5 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -69,7 +69,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 43bae3c..9efda6f 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index b25d78e..b2e3356 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -41,7 +41,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
- int lidswitch=0; + int lidswitch = 0; if (!gpio_base) return;
diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index caf8b4a..46d3e86 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -37,32 +37,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x103C18F9),
/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
/* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140),
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 2c5170d..dd2f7b5 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -225,7 +225,7 @@ static void mainboard_init(device_t dev) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index c2e9e79..6ab0063 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -113,9 +113,9 @@ void mainboard_fill_spd_data(struct pei_data *ps)
/* * Set SPD and memory configuration: - * Memory type: 0=DimmInstalled, - * 1=SolderDownMemory, - * 2=DimmDisabled + * Memory type: 0 = DimmInstalled, + * 1 = SolderDownMemory, + * 2 = DimmDisabled */ if (spd_content != NULL) { ps->spd_data_ch0 = spd_content; diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index 34de87a..6ea2284 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -25,14 +25,14 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin
# Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000) -SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001) -SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID=010) -SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID=011) -SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID=100) -SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101) -SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110) -SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111) +SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID = 000) +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID = 001) +SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID = 010) +SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID = 011) +SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID = 100) +SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID = 101) +SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID = 110) +SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID = 111)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c index 041c3f0..fa292ad 100644 --- a/src/mainboard/google/guado/lan.c +++ b/src/mainboard/google/guado/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/guado/romstage.c b/src/mainboard/google/guado/romstage.c index 24acc80..3ae31f0 100644 --- a/src/mainboard/google/guado/romstage.c +++ b/src/mainboard/google/guado/romstage.c @@ -57,8 +57,8 @@ void mainboard_pre_console_init(void)
/* Turn On GPIO10.LED */ it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
} diff --git a/src/mainboard/google/guado/smihandler.c b/src/mainboard/google/guado/smihandler.c index d37cc33..0118e6b 100644 --- a/src/mainboard/google/guado/smihandler.c +++ b/src/mainboard/google/guado/smihandler.c @@ -62,14 +62,14 @@ void mainboard_smi_sleep(u8 slp_typ) switch (slp_typ) { case ACPI_S3: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x01 /* polarity */, 0x01 /* 1=pullup */, - 0x01 /* output */, 0x00, /* 0=Alternate function */ + 0x01 /* polarity */, 0x01 /* 1 = pullup */, + 0x01 /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; default: diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 651c8e6..e76994f 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 5ebb42d..0f8e0f2 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -116,8 +116,8 @@ struct iodef iodefs[] = { {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, - {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, - {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, + {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x00000000, 0}, + {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, {R, 1, "", _DSPAADDR, 0x00000000, 0}, {W, 1, "", _DSPAADDR, 0x00000000, 0}, {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, @@ -194,15 +194,15 @@ struct iodef iodefs[] = { {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x40000000, 0}, + {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x40000000, 0}, + {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, {R, 1, "", 0x145d10, 0x2010040c, 0}, {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, @@ -271,8 +271,8 @@ struct iodef iodefs[] = { {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, + {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, {R, 1, "", _DSPAADDR, 0x00000000, 0}, {W, 1, "", _DSPAADDR, 0x00000000, 0}, {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, diff --git a/src/mainboard/google/ninja/lan.c b/src/mainboard/google/ninja/lan.c index dad8692..cea30e8 100644 --- a/src/mainboard/google/ninja/lan.c +++ b/src/mainboard/google/ninja/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 202d8d0..91d882f 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 4cc72f1..f6e785c 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -138,18 +138,18 @@ static const struct parade_write parade_writes[] = { { 0x04, 0x71, 0x2d }, /* * 2.7G CDR settings - * NOF=40LSB for HBR CDR setting + * NOF = 40LSB for HBR CDR setting */ { 0x04, 0x7d, 0x07 }, { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */ { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */ /* * 1.62G CDR settings - * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 + * [5:2]NOF = 64LSB [1:0]DCO scale is 2/5 */ { 0x04, 0xc0, 0x12 }, { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */ - { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */ + { 0x04, 0xc2, 0x1c }, /* Fbstep = 100% */ { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */ /* * RPIO Setting diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c index e5676af..6099bc1 100644 --- a/src/mainboard/google/rikku/lan.c +++ b/src/mainboard/google/rikku/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c index 5f06ed9..b626bdd 100644 --- a/src/mainboard/google/rikku/romstage.c +++ b/src/mainboard/google/rikku/romstage.c @@ -56,8 +56,8 @@ void mainboard_pre_console_init(void)
/* Turn On GPIO10.LED */ it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
} diff --git a/src/mainboard/google/rikku/smihandler.c b/src/mainboard/google/rikku/smihandler.c index 4331a1f..4649411 100644 --- a/src/mainboard/google/rikku/smihandler.c +++ b/src/mainboard/google/rikku/smihandler.c @@ -61,14 +61,14 @@ void mainboard_smi_sleep(u8 slp_typ) switch (slp_typ) { case ACPI_S3: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x01 /* polarity */, 0x01 /* 1=pullup */, - 0x01 /* output */, 0x00, /* 0=Alternate function */ + 0x01 /* polarity */, 0x01 /* 1 = pullup */, + 0x01 /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - 0x01 /* output */, 0x01 /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + 0x01 /* output */, 0x01 /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; default: diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 4e3839f..ca67759 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -52,7 +52,7 @@ static void mainboard_init(device_t dev) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ ethernet_dev = dev_find_device(STOUT_NIC_VENDOR_ID, STOUT_NIC_DEVICE_ID, dev); diff --git a/src/mainboard/google/tidus/lan.c b/src/mainboard/google/tidus/lan.c index 7c03f6c..08205cc 100644 --- a/src/mainboard/google/tidus/lan.c +++ b/src/mainboard/google/tidus/lan.c @@ -162,7 +162,7 @@ void lan_init(void) /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN pci config space 0x81h = 01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/tidus/led.c b/src/mainboard/google/tidus/led.c index c0bf332..4c605e6 100644 --- a/src/mainboard/google/tidus/led.c +++ b/src/mainboard/google/tidus/led.c @@ -27,9 +27,9 @@ void set_power_led(u8 led_pin_map, int state) 1 /* set */, 0x01 /* select */, state /* polarity: non-inverting */, - 0x00 /* 0=pulldown */, + 0x00 /* 0 = pulldown */, 0x01 /* output */, - 0x01 /* 1=Simple IO function */, + 0x01 /* 1 = Simple IO function */, led_pin_map, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; @@ -38,9 +38,9 @@ void set_power_led(u8 led_pin_map, int state) 1 /* set */, 0x01 /* select */, 0x01 /* polarity */, - 0x01 /* 1=pullup */, + 0x01 /* 1 = pullup */, 0x01 /* output */, - 0x00, /* 0=Alternate function */ + 0x00, /* 0 = Alternate function */ led_pin_map, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index c85f380..47e0a3a 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -25,7 +25,7 @@
unsigned long acpi_fill_madt(unsigned long current) { - unsigned int gsi_base=0x18; + unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c index fb0c62b..877cb5b 100644 --- a/src/mainboard/hp/dl145_g1/fadt.c +++ b/src/mainboard/hp/dl145_g1/fadt.c @@ -24,13 +24,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x04; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x04; + fadt->sci_int = 9;
// disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; @@ -59,8 +59,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state - fadt->flush_size = 0; // ignored if wbindv=1 in flags - fadt->flush_stride = 0; // ignored if wbindv=1 in flags + fadt->flush_size = 0; // ignored if wbindv = 1 in flags + fadt->flush_stride = 0; // ignored if wbindv = 1 in flags fadt->duty_offset = 1; fadt->duty_width = 3; // 0 means duty cycle not supported // _alrm value 0 means RTC alarm feature not supported diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index 9c35814..da02095 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -52,7 +52,7 @@ void get_bus_conf(void) device_t dev; int i;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -60,7 +60,7 @@ void get_bus_conf(void) struct mb_sysconf_t *m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 8b5b428..17aad3c 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -53,11 +53,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { int ret,i; unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); smbus_write_byte(SMBUS_HUB, 0x03, 0); }
@@ -65,11 +65,11 @@ static inline void change_i2c_mux(unsigned device) { int ret, i; printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device); - i=2; + i = 2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret); - } while ((ret!=0) && (i-->0)); + } while ((ret != 0) && (i-->0)); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); } @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { /* Read FIDVID_STATUS */ msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); }
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); }
@@ -173,10 +173,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus();
int i; - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { activate_spd_rom(&sysinfo->ctrl[i]); } - for(i=RC0;i<=RC1;i<<=1) { + for(i = RC0; i <= RC1; i<<=1) { change_i2c_mux(i); }
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index 87f065d..d69e224 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -78,7 +78,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -125,6 +125,6 @@ void get_bus_conf(void) apicid_base = get_apicid_base(3); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - for(i=0;i<3;i++) + for(i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 5aeb71d..716c783 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric W.Biedermanebiderman@lnxi.com + * Copyright (C) 2001 Eric W.Biederman ebiderman@lnxi.com * * Copyright (C) 2006 AMD * Written by Yinghai Lu yinghailu@gmail.com for AMD. @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) device_t dev = 0; int i; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 12d18cf..fc1ba08 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -91,19 +91,19 @@ static void setup_early_ipmi_serial() // earlydbg(result); /* //Set serial/modem config - result=ipmi_request(6,serialmodem_conf); + result = ipmi_request(6,serialmodem_conf); earlydbg(result);
//Set serial mux 1 - result=ipmi_request(4,serial_mux1); + result = ipmi_request(4,serial_mux1); earlydbg(result);
//Set serial mux 2 - result=ipmi_request(4,serial_mux2); + result = ipmi_request(4,serial_mux2); earlydbg(result);
//Set serial mux 3 - result=ipmi_request(4,serial_mux3); + result = ipmi_request(4,serial_mux3); earlydbg(result); */ // earlydbg(0x0e); @@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index e323873..68c3881 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) int i; struct mb_sysconf_t *m;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -80,7 +80,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -124,6 +124,6 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/ apicid_base = 0x10; - for(i=0;i<3;i++) + for(i = 0; i < 3; i++) m->apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 395de57..7d0611a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric W.Biedermanebiderman@lnxi.com + * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com> * * Copyright (C) 2006 AMD * Written by Yinghai Lu yinghailu@gmail.com for AMD. @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) device_t dev = 0; int i; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 84e28f7..39cd0e3 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9d2b90a..3fa339f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -87,14 +87,14 @@ static void early_superio_config_w83627ehg(void) pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
- dev=PNP_DEV(0x4e, W83627EHG_SP1); + dev = PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627EHG_SP2); + dev = PNP_DEV(0x4e, W83627EHG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); @@ -102,7 +102,7 @@ static void early_superio_config_w83627ehg(void) // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); @@ -110,27 +110,27 @@ static void early_superio_config_w83627ehg(void) //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627EHG_GPIO2); + dev = PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it
- dev=PNP_DEV(0x4e, W83627EHG_GPIO3); + dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
- dev=PNP_DEV(0x4e, W83627EHG_FDC); + dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x4e, W83627EHG_PP); + dev = PNP_DEV(0x4e, W83627EHG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0);
/* Enable HWM */ - dev=PNP_DEV(0x4e, W83627EHG_HWM); + dev = PNP_DEV(0x4e, W83627EHG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index ebb0e20..f65c833 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -51,7 +51,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard Kino Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 7b00176..09e4ec7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 56ca33a..1afc517 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -144,7 +144,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { 0x10EC0262, /* Vendor ID/Device IDA */ 0x0000, /* SubSystem ID */ 0xFF, /* Revision IDA */ - 0x01, /* Front panel support (1=yes, 2=no) */ + 0x01, /* Front panel support (1 = yes, 2 = no) */ 0x000B, /* Number of Rear Jacks = 11 */ 0x0002 /* Number of Front Jacks = 2 */ }, diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index 608489b..79ca0a4 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -61,13 +61,13 @@ static inline void siodump(void) unsigned char data;
printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { + for (i = 0x10; i <= 0x2d; i++) { print_reg((unsigned char)i); } #if 0 printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { + for (i = 0xf0; i <= 0xff; i++) { print_reg((unsigned char)i); }
@@ -82,7 +82,7 @@ static inline void siodump(void) #endif printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n"); setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { + for (i = 0xf0; i <= 0xf8; i++) { print_reg((unsigned char)i); } printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n"); diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index d0f1b1f..b17f57c 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -175,7 +175,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */ GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */ GPIO_NC, /* GPIO_S5[04] - No Connect */ - GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/ + GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0 = 1GB 1 = 2GB or 4GB*/ GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ diff --git a/src/mainboard/intel/stargo2/gpio.h b/src/mainboard/intel/stargo2/gpio.h index 25ecfeb..9651655 100644 --- a/src/mainboard/intel/stargo2/gpio.h +++ b/src/mainboard/intel/stargo2/gpio.h @@ -165,9 +165,9 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio37 = GPIO_MODE_NONE, /* Unused */ .gpio38 = GPIO_MODE_GPIO, /* Dev Kit Board Version high bit */ .gpio39 = GPIO_MODE_GPIO, /* Dev Kit Board Version low bit */ - .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N<1> */ - .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N<2> */ - .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N<3> */ + .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N <1> */ + .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N <2> */ + .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N <3> */ .gpio43 = GPIO_MODE_NONE, /* Unused */ .gpio44 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO1_SUS : MLR TODO */ .gpio45 = GPIO_MODE_NONE, /* Unused */ @@ -184,7 +184,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio56 = GPIO_MODE_GPIO, /* CONN_GBE_RESET_N */ .gpio57 = GPIO_MODE_NONE, /* Unused */ .gpio58 = GPIO_MODE_NATIVE, /* PCH_SML1_CLK */ - .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N<0> */ + .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N <0> */ .gpio60 = GPIO_MODE_NONE, /* Unused */ .gpio61 = GPIO_MODE_NATIVE, /* PCH_SUS_STAT_N */ .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK */ diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc index 6ef4fc9..9bb53a5 100644 --- a/src/mainboard/intel/truxton/Makefile.inc +++ b/src/mainboard/intel/truxton/Makefile.inc @@ -1 +1 @@ -ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 +ROMCCFLAGS := -mcpu = p4 -fno-simplify-phi -O2 diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 9750d08..a5c0c9c 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -219,7 +219,7 @@ void transaction3(unsigned char dev_addr)
// sch_SMbus_regs (); //check the status register for busy state - //temp=inb(SMBusBase+SMBHSTSTS); + //temp = inb(SMBusBase+SMBHSTSTS); //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp); //sch_SMbus_regs (); //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS)); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 7c8835a..5b2b2b0 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -24,7 +24,7 @@
unsigned long acpi_fill_madt(unsigned long current) { - unsigned int gsi_base=0x18; + unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -66,7 +66,7 @@ unsigned long acpi_fill_madt(unsigned long current) int i; int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -144,11 +144,11 @@ unsigned long mainboard_write_acpi_tables(device_t device,
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; uint8_t c; - if(i<7) { + if(i < 7) { c = (uint8_t) ('4' + i - 1); } else { diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c index 43d7c16..c7d649a 100644 --- a/src/mainboard/iwill/dk8_htx/fadt.c +++ b/src/mainboard/iwill/dk8_htx/fadt.c @@ -23,13 +23,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision=0; + header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->dsdt= (u32)dsdt; - // 3=Workstation,4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile=0x03; - fadt->sci_int=9; + // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index eecad5c..b7c21e4 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) { @@ -93,28 +93,28 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
//Slot 5 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 }
//Slot 6 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 } //Slot 1: HTX
//Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30 }
//Slot 3 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 }
//Slot 4 PCI-X 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 }
@@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v)
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { + for(i = 1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; device_t dev; @@ -140,7 +140,7 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { + for(ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // } } @@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { + for(ii = 0; ii < 4; ii++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 } } diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 4cf89b1..e269475 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 0de239c..c7e2fe9 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -53,7 +53,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
- /* bit=0 means enable function (per CX700 datasheet) + /* bit = 0 means enable function (per CX700 datasheet) * 5 16.1 USB 2 * 4 16.0 USB 1 * 3 15.0 SATA and PATA @@ -62,7 +62,7 @@ static void enable_mainboard_devices(void) */ pci_write_config8(dev, 0x50, 0x80);
- /* bit=1 means enable internal function (per CX700 datasheet) + /* bit = 1 means enable internal function (per CX700 datasheet) * 3 Internal RTC * 2 Internal PS2 Mouse * 1 Internal KBC Configuration diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 37caa6e..9956d98 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -66,7 +66,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8(0xCD6, 0x27); Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; + Data16 = Data8<<8; WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 0db35ce..895057b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -134,7 +134,7 @@ chip northbridge/amd/agesa/family14/root_complex # # TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD # with i2cdump tool. -# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. +# Notes: 0xa0 = 0x50*2, 0xa2 = 0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. # register "spdAddrLookup" = " { diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index fe22283..d4d489c 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -98,7 +98,7 @@ u8 is_dev3_present(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev = 0x%p\n", dev);
set_pcie_dereset(); /* get_ide_dma66(); */ diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 8c87563..43e88d1 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 3dcf4cc..afcbd47 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -98,7 +98,7 @@ static void early_superio_config_w83627thg(void) { device_t dev;
- dev=PNP_DEV(0x2e, W83627THG_SP1); + dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc6); // PNPCSV @@ -106,14 +106,14 @@ static void early_superio_config_w83627thg(void) pnp_write_config(dev, 0x29, 0x43); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
- dev=PNP_DEV(0x2e, W83627THG_SP1); + dev = PNP_DEV(0x2e, W83627THG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_SP2); + dev = PNP_DEV(0x2e, W83627THG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); @@ -121,7 +121,7 @@ static void early_superio_config_w83627thg(void) // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_KBC); + dev = PNP_DEV(0x2e, W83627THG_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); @@ -129,33 +129,33 @@ static void early_superio_config_w83627thg(void) // pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); + dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_GPIO2); + dev = PNP_DEV(0x2e, W83627THG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it
- dev=PNP_DEV(0x2e, W83627THG_GPIO3); + dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
- dev=PNP_DEV(0x2e, W83627THG_FDC); + dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x2e, W83627THG_PP); + dev = PNP_DEV(0x2e, W83627THG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0);
/* Enable HWM */ - dev=PNP_DEV(0x2e, W83627THG_HWM); + dev = PNP_DEV(0x2e, W83627THG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); @@ -163,7 +163,7 @@ static void early_superio_config_w83627thg(void)
pnp_exit_func_mode(dev);
- dev=PNP_DEV(0x4e, W83627THG_SP1); + dev = PNP_DEV(0x4e, W83627THG_SP1); pnp_enter_func_mode(dev);
pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values @@ -172,22 +172,22 @@ static void early_superio_config_w83627thg(void) pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627THG_SP2); + dev = PNP_DEV(0x4e, W83627THG_SP2); pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 10); pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627THG_FDC); + dev = PNP_DEV(0x4e, W83627THG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x4e, W83627THG_PP); + dev = PNP_DEV(0x4e, W83627THG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x4e, W83627THG_KBC); + dev = PNP_DEV(0x4e, W83627THG_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c index f9768b2..8888f98 100644 --- a/src/mainboard/kontron/kt690/fadt.c +++ b/src/mainboard/kontron/kt690/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index f01e521..3886f9f 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -71,7 +71,7 @@ static void enable_onboard_nic(void) /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */ byte = inb(0xC51); byte &= 0x3F; - byte |= 0x80; /* 7:6=10 */ + byte |= 0x80; /* 7:6 = 10 */ outb(byte, 0xC51);
/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */ @@ -178,7 +178,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard KT690 Enable. dev = 0x%p\n", dev);
enable_onboard_nic(); get_ide_dma66(); diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index cb33e3b..6afe2c0 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_kt690_resource_map();
@@ -111,16 +111,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx); @@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); diff --git a/src/mainboard/lenovo/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/hda_verb.c index ee54874..4378341 100644 --- a/src/mainboard/lenovo/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/hda_verb.c @@ -38,32 +38,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x17AA21FB),
/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
/* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 154b314..18094c2 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -38,32 +38,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x17AA21FA),
/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
/* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 792579a..cc9e02d 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -38,32 +38,32 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0x0, 0x17AA21FA),
/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
/* NID 0x0F - Not connected - * Config=0x40F000F0 + * Config = 0x40F000F0 */ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) */ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 79c093f..a8cf5c5 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -31,7 +31,7 @@
/* Init SIO GPIOs. */ #define SIO_RUNTIME_BASE 0x0E00 -static const u16 sio_init_table[] = { // hi=offset, lo=value +static const u16 sio_init_table[] = { // hi = offset, lo = value 0x4BA0, // GP1x: COM1/2 control = RS232, no term, max 115200 0x2300, // GP10: COM1 termination = push/pull output 0x2400, // GP11: COM2 termination = push/pull output @@ -70,7 +70,7 @@ static const u16 sio_init_table[] = { // hi=offset, lo=value static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) { __outbyte(SMB0_STATUS, 0x1E); // clear error status - __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out + __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction = out __outbyte(SMB0_HOSTCMD, command); // or destination offset __outbyte(SMB0_DATA0, length); // sent before data __inbyte(SMB0_CONTROL); // reset block data array diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c index ffd20d0..3d32113 100644 --- a/src/mainboard/lippert/hurricane-lx/mainboard.c +++ b/src/mainboard/lippert/hurricane-lx/mainboard.c @@ -31,7 +31,7 @@ #define SIO_GP1X_CONFIG 0x00 #endif
-static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ 0x805C, /* Unlock zero adjust */ diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 0c9e03a..7e3288f 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -76,7 +76,7 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c"
-static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -84,7 +84,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins - 0xBF27, 0xFF28, 0x2D29, // (GP36=FAN_CTL3 (PWM), GP23,22,16,15=SPI, GP13=PWROK1) + 0xBF27, 0xFF28, 0x2D29, // (GP36 = FAN_CTL3 (PWM), GP23,22,16,15 = SPI, GP13 = PWROK1) 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE 0x06C8, // config GP12,11 as output, GP10 as input diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c index 1a569e2..e4084b5 100644 --- a/src/mainboard/lippert/literunner-lx/mainboard.c +++ b/src/mainboard/lippert/literunner-lx/mainboard.c @@ -34,7 +34,7 @@ /* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */ #define SIO_GP2X_CONFIG 0x00
-static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index efe322c..2f6aa46 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -115,7 +115,7 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c"
-static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -123,7 +123,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins - 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) + 0xFF27, 0xDF28, 0x2729, // (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1) 0x66B8, 0x0FB9, // enable pullups on SPI, RS485_EN, COM3_R/TX_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED 0x03C1, // enable Simple-I/O for GP21-20= COM3_RX_EN,TX_EN @@ -131,7 +131,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x07C8, // config GP12-10 as output 0x03C9, // config GP21-20 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55 - 0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use) + 0x08F8, // map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use) };
/* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c index cd83768..1d35ebe 100644 --- a/src/mainboard/lippert/roadrunner-lx/mainboard.c +++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c @@ -31,7 +31,7 @@ #define SIO_GP1X_CONFIG 0x20 #endif
-static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ 0x805C, /* Unlock zero adjust */ diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index d70e2c1..7e0e2a5 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -52,7 +52,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c"
-static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset 0x9072, // watchdog triggers PWROK, counts seconds @@ -60,13 +60,13 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins - 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) + 0xBF27, 0xFF28, 0x2529, // (GP36 = FAN_CTL3, GP13 = PWROK1) 0x46B8, 0x0CB9, // enable pullups on RS485_EN 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) 0x26C8, // config GP15,12,11 as output; GP14 as input 0x2DF5, // map Hw Monitor Thermal Output to GP55 - 0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use) + 0x0DF8, // map GP LED Blinking 1 to GP15 = LIVE_LED (deactivate Simple-I/O to use) };
/* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c index 4decd0e..b0bc74e 100644 --- a/src/mainboard/lippert/spacerunner-lx/mainboard.c +++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c @@ -31,7 +31,7 @@ #define SIO_GP1X_CONFIG 0x01 #endif
-static const u16 ec_init_table[] = { /* hi=data, lo=index */ +static const u16 ec_init_table[] = { /* hi = data, lo = index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index b3a13ad..85503c5 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -116,7 +116,7 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c"
-static const u16 sio_init_table[] = { // hi=data, lo=index +static const u16 sio_init_table[] = { // hi = data, lo = index 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -124,12 +124,12 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins - 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) + 0xFF27, 0xDF28, 0x2729, // (GP45 = SUSB, GP23,22,16,15 = SPI, GP13 = PWROK1) 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED 0x07C8, // config GP12-10 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55 - 0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use) + 0x08F8, // map GP LED Blinking 1 to GP10 = LIVE_LED (deactivate Simple I/O to use) };
/* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index b9c532f..6b51fd2 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -39,7 +39,7 @@ static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) { __outbyte(SMB0_STATUS, 0x1E); // clear error status - __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out + __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction = out __outbyte(SMB0_HOSTCMD, command); // or destination offset __outbyte(SMB0_DATA0, length); // sent before data __inbyte(SMB0_CONTROL); // reset block data array @@ -96,7 +96,7 @@ static void init(struct device *dev) * effect a power cycle and switch to the alternate BIOS chip. * Should be done as late as possible. */ printk(BIOS_INFO, "Sending BIOS alive message\n"); - const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS + const u8 i_am_alive[] = { 0x03 }; //bit2 = SEL_DP0: 0 = DDI2, 1 = LVDS if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive))) printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 775fdc6c..2956e2d 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2001 Eric W.Biedermanebiderman@lnxi.com + * Copyright (C) 2001 Eric W.Biederman ebiderman@lnxi.com * * Copyright (C) 2006 AMD * Written by Yinghai Lu yinghailu@gmail.com for AMD. @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) { device_t dev = 0; struct resource *res; - for(i=0; i<3; i++) { + for(i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
//USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i=0;i<3;i++) { + for(i = 0; i < 3; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // }
@@ -101,13 +101,13 @@ static void *smp_write_config_table(void *v)
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 // AIC 8130 Galileo Technology... - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // }
//pci slot (on bcm5785) - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); // }
@@ -116,29 +116,29 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // }
//onboard Broadcom - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // }
// First PCI-E x8 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); // }
// Second PCI-E x8 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); // }
// Third PCI-E x1 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); // }
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index f6f6859..b73d76c 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0 int i; - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { activate_spd_rom(sysinfo->ctrl+i); dump_smbus_registers(); } diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index cbad735..c034294 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -99,15 +99,15 @@ static void *smp_write_config_table(void *v) //NIC2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 39a24dd..0614e1f 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void)
printk(BIOS_SPEW, "get_bus_conf()\n");
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -80,7 +80,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -99,7 +99,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); }
- for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -112,10 +112,10 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } else { apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base); + printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base); } m->apicid_mcp55 = apicid_base+0; } diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index eff19c7..73b4c0f 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3af4785..c5caf14 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); /* Need to use TMICT to synchronize FID/VID. */ diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index cfe5beb..6b34c50 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 6a9b26c..d5a2b70 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -240,7 +240,7 @@ void m3885_configure_multikey(void) m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
/* Write Matrix to bank 0 */ - for (i=0; i < ARRAY_SIZE(matrix); i++) { + for (i = 0; i < ARRAY_SIZE(matrix); i++) { m3885_set_proc_ram(i + 0x80, matrix[i]); }
@@ -257,7 +257,7 @@ void m3885_configure_multikey(void) printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs); } else { printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs); - for (i=0; i < ARRAY_SIZE(function_ram); i++) { + for (i = 0; i < ARRAY_SIZE(function_ram); i++) { m3885_set_proc_ram(i + offs, function_ram[i]); } } @@ -269,7 +269,7 @@ void m3885_configure_multikey(void) m3885_set_variable(0x0c, kstate5_flags); maxvars = m3885_get_variable(0x00); printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars); - for (i=0; i<ARRAY_SIZE(variables); i+=3) { + for (i = 0; i < ARRAY_SIZE(variables); i+=3) { if(variables[i + 0] > maxvars) continue; reg8 = m3885_get_variable(variables[i + 0]); diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 1ef2497..1959c32 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -35,7 +35,7 @@ static void backlight_enable(void) /* P56 is Brightness Up, and it needs a Pulse instead of a * Level */ - for (i=0; i < 28; i++) { + for (i = 0; i < 28; i++) { //m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56); m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56); } @@ -49,10 +49,10 @@ static void dump_runtime_registers(void) int i;
printk(BIOS_DEBUG, "SuperIO runtime register block:\n"); - for (i=0; i<0x10; i++) + for (i = 0; i < 0x10; i++) printk(BIOS_DEBUG, "%02x ", i); printk(BIOS_DEBUG, "\n"); - for (i=0; i<0x10; i++) + for (i = 0; i < 0x10; i++) printk(BIOS_DEBUG, "%02x ", inb(0x600 +i)); printk(BIOS_DEBUG, "\n"); } diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index f3af5fa..4723885 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -113,7 +113,7 @@ static void early_superio_config(void) { device_t dev;
- dev=PNP_DEV(0x2e, 0x00); + dev = PNP_DEV(0x2e, 0x00);
pnp_enter_ext_func_mode(dev); pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c index 8e8b936..9d07e64 100644 --- a/src/mainboard/samsung/lumpy/gpio.c +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -233,9 +233,9 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio41 = GPIO_LEVEL_LOW, .gpio42 = GPIO_LEVEL_LOW, .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB0 SDP */ - .gpio45 = GPIO_LEVEL_LOW, /* CTL3=0 for USB0 SDP */ - .gpio46 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB1 SDP */ + .gpio44 = GPIO_LEVEL_HIGH, /* CTL2 = 1 for USB0 SDP */ + .gpio45 = GPIO_LEVEL_LOW, /* CTL3 = 0 for USB0 SDP */ + .gpio46 = GPIO_LEVEL_HIGH, /* CTL2 = 1 for USB1 SDP */ .gpio47 = GPIO_LEVEL_HIGH, /* Enable USB0 */ .gpio48 = GPIO_LEVEL_LOW, /* Disable Bluetooth */ .gpio49 = GPIO_LEVEL_LOW, @@ -299,7 +299,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio70 = GPIO_LEVEL_HIGH, /* WLAN out of reset */ .gpio71 = GPIO_LEVEL_HIGH, /* WLAN power on */ .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3=0 for SDP */ + .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3 = 0 for SDP */ .gpio74 = GPIO_LEVEL_LOW, .gpio75 = GPIO_LEVEL_LOW, }; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 738f1ff..c2d74ee 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -145,8 +145,8 @@ static void setup_sio_gpios(void) * GPIO45 as LED_POWER# */ it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - (0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + (0x1<<5) /* output */, (0x1<<5) /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
/* diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 215af8f..25f4ab9 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -37,15 +37,15 @@ void mainboard_smi_sleep(u8 slp_typ) case ACPI_S3: case ACPI_S4: it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, - (0x1<<5) /* polarity */, (0x1<<5) /* 1=pullup */, - (0x1<<5) /* output */, 0x00, /* 0=Alternate function */ + (0x1<<5) /* polarity */, (0x1<<5) /* 1 = pullup */, + (0x1<<5) /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break;
case ACPI_S5: it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, - (0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, + (0x1<<5) /* output */, (0x1<<5) /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; default: diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index c8cc66b..15d949e 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -145,7 +145,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { 0x10EC0262, /* Vendor ID/Device IDA */ 0x0000, /* SubSystem ID */ 0xFF, /* Revision IDA */ - 0x01, /* Front panel support (1=yes, 2=no) */ + 0x01, /* Front panel support (1 = yes, 2 = no) */ 0x000B, /* Number of Rear Jacks = 11 */ 0x0002 /* Number of Front Jacks = 2 */ }, diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c index 7d7221d..80468ed 100644 --- a/src/mainboard/siemens/sitemp_g1p1/fadt.c +++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c @@ -57,7 +57,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 41811e4..8c65972 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -657,7 +657,7 @@ static void update_subsystemid( device_t dev ) dev->subsystem_device = 0x4077; // U1P0 = 0x4077 } printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device ); - for( i=0; slot[i].bus < 255; i++) { + for( i = 0; slot[i].bus < 255; i++) { device_t d; d = dev_find_slot(slot[i].bus,slot[i].devfn); if( d ) { diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index 1ae48f3..12c94a1 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc);
get_bus_conf(); - printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600); + printk(BIOS_DEBUG, "%s: apic_id = 0x%x\n", __func__, apicid_sb600);
mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 634f974..c0dda4e 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid); + __DEBUG__("bsp_apicid = 0x%x\n", bsp_apicid);
setup_sitemp_resource_map();
@@ -141,16 +141,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if( (cpuid1.edx & 0x6) == 0x6 ) {
/* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + __DEBUG__("begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + __DEBUG__("end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
} else { __DEBUG__("Changing FIDVID not supported\n"); @@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - __DEBUG__("needs_reset=0x%x\n", needs_reset); + __DEBUG__("needs_reset = 0x%x\n", needs_reset);
post_code(0x06);
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index eeae519..f5e4145 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -139,7 +139,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
//Slot 1 PCIE x16 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); }
@@ -147,16 +147,16 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
//Slot 2 PCI 32 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); }
if(pci1234[2] & 0xf) { //Onboard ck804b NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21 = 53
//Slot 3 PCIE x16 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); } } @@ -164,24 +164,24 @@ static void *smp_write_config_table(void *v) //Channel B of 8131
//Slot 4 PCI-X 100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4); }
//Slot 5 PCIX 100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29 }
//OnBoard LSI SCSI - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30 }
//Channel A of 8131
//Slot 6 PCIX 133/100/66 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 }
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 7a5ce93..bb610d1 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index bf8f0da..d536a50 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -91,24 +91,24 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); }
if(bus_pcix[0]) { - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 }
- for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 } } diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index eda7dc6..1538092 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -92,24 +92,24 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); }
if(bus_pcix[0]) { - for(i=0;i<2;i++) { + for(i = 0; i < 2; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 }
- for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 } } diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index eb73817..851233e 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 6739105..8a0a6ec 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) device_t dev; int i;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -79,7 +79,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -98,7 +98,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); }
- for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index e1ca607..b238745 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index c568334..ac978a1 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -53,7 +53,7 @@ static UINT8 select_socket(UINT8 socket_id) gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL); value = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK); value |= socket_id; - value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0=Output Enabled, 1=Tristate + value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0 = Output Enabled, 1 = Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value);
return gpio56_to_53; diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index f4fe61e..ae6991f 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 5a7157b..813fa77 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) device_t dev; int i;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -81,7 +81,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -104,7 +104,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); }
- for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index e4dd3a8..180a34d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
- for(j=7;j>=2; j--) { + for(j = 7;j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 4661f45..7070af9 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c index 330dc54..fda488f 100644 --- a/src/mainboard/supermicro/h8scm/fadt.c +++ b/src/mainboard/supermicro/h8scm/fadt.c @@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index 08910cc..b50410a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; - u32 gsi_base=0; + u32 gsi_base = 0; /* create all subtables for processors */ current = acpi_create_madt_lapics(current);
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 42f80e4..13c2a2c 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard H8SCM Enable. dev = 0x%p\n", dev);
msr_t msr, msr2;
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 7312683..f2c79b4 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c index f9768b2..8888f98 100644 --- a/src/mainboard/technexion/tim5690/fadt.c +++ b/src/mainboard/technexion/tim5690/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index f84b7a0..e2530fe 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -226,7 +226,7 @@ static void mainboard_enable(device_t dev) u8 port2; #endif
- printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard tim5690 Enable. dev = 0x%p\n", dev);
mb_gpio_init(&gpio_base);
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index b94b06c..63eaee6 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -92,7 +92,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_tim5690_resource_map();
@@ -116,16 +116,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } @@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c index 1fa4935..621e182 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.c +++ b/src/mainboard/technexion/tim5690/tn_post_code.c @@ -36,7 +36,7 @@ void technexion_post_code_init(void) { uint8_t reg8_data; - device_t dev=0; + device_t dev = 0;
// SMBus Module and ACPI Block (Device 20, Function 0) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); @@ -129,7 +129,7 @@ void technexion_post_code_init(void) void technexion_post_code(uint8_t udata8) { uint8_t u8_data; - device_t dev=0; + device_t dev = 0;
// SMBus Module and ACPI Block (Device 20, Function 0) #ifdef __PRE_RAM__ diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c index f9768b2..8888f98 100644 --- a/src/mainboard/technexion/tim8690/fadt.c +++ b/src/mainboard/technexion/tim8690/fadt.c @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 939becf..a7de119 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -59,7 +59,7 @@ static void enable_onboard_nic(void) byte |= ( 1 << 7); pci_write_config8(sm_dev, 0x9a, byte);
- byte=pm_ioread(0x59); + byte = pm_ioread(0x59); byte &= ~( 1<< 5); pm_iowrite(0x59,byte);
@@ -138,7 +138,7 @@ static void set_thermal_config(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard tim8690 Enable. dev = 0x%p\n", dev);
enable_onboard_nic(); set_thermal_config(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index e052d92..e36d4b3 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid = 0x%x\n", bsp_apicid);
setup_tim8690_resource_map();
@@ -111,16 +111,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6 ) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } @@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + printk(BIOS_DEBUG, "needs_reset = 0x%x\n", needs_reset);
if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index c387ac6..bdcc1fa 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -67,7 +67,7 @@ static void flash_gpios(void) if ((manufacturer_id == 0x20) && ((device_id == 0x2c) || (device_id == 0x2d))) { printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n", - (device_id==0x2c)?'4':'8'); + (device_id == 0x2c)?'4':'8'); u8 fgpi = read8((u8 *)0xffbc0100); printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n", (fgpi & (1 << 0)) ? 'X' : ' ', diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index 0bc852e..d13f737 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) device_t dev; int i;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -77,7 +77,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -96,7 +96,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); }
- for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index c878160..56bb9a9 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index c80e2d6..febc0c8 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 9d633a3..29ab03d 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) device_t dev; int i;
- if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -78,7 +78,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -97,7 +97,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); }
- for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index 157b363..0626df2 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -86,15 +86,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
- for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } }
- for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); }
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index bd64cab..d554396 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A);
/* show final fid and vid */ - msr=rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif
diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 0fa9742..119821f 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -53,13 +53,13 @@ static UINT8 select_socket(UINT8 socket_id) */ gpio52_to_49 = pci_read_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL); value = gpio52_to_49 | GPIO_OUT_BIT_GPIO49; // Output of GPIO49 is always forced to "1" - value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0=Output Enabled, 1=Tristate + value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0 = Output Enabled, 1 = Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, value);
value = pci_read_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL); value &= ~(GPIO_OUT_BIT_GPIO48); value |= (~(socket_id & 1)) << 3; // Output of GPIO48 is inverse of SocketId - value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0=Output Enabled, 1=Tristate + value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0 = Output Enabled, 1 = Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, value);
return gpio52_to_49; diff --git a/src/mainboard/tyan/s8226/fadt.c b/src/mainboard/tyan/s8226/fadt.c index 330dc54..fda488f 100644 --- a/src/mainboard/tyan/s8226/fadt.c +++ b/src/mainboard/tyan/s8226/fadt.c @@ -55,7 +55,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) else fadt->dsdt = (uintptr_t)dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; /* disable system management mode by setting to 0: */ diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index a28bf78..39dd3fc 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -46,7 +46,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
- /* bit=0 means enable function (per CX700 datasheet) + /* bit = 0 means enable function (per CX700 datasheet) * 5 16.1 USB 2 * 4 16.0 USB 1 * 3 15.0 SATA and PATA @@ -55,7 +55,7 @@ static void enable_mainboard_devices(void) */ pci_write_config8(dev, 0x50, 0x80);
- /* bit=1 means enable internal function (per CX700 datasheet) + /* bit = 1 means enable internal function (per CX700 datasheet) * 3 Internal RTC * 2 Internal PS2 Mouse * 1 Internal KBC Configuration diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 1a5685f..77bc884 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -77,12 +77,12 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); }
//Slot PCIE x4 - for(i=0;i<4;i++) { + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); }
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 20eb92e..95edddd 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -109,13 +109,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr_t msr; /* Read FIDVID_STATUS */ msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "begin msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo);
enable_fid_change(); init_fidvid_bsp(bsp_apicid);
msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "end msr fid, vid: hi = 0x%x, lo = 0x%x\n", msr.hi, msr.lo); } #endif