Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56926 )
Change subject: mb/google/brya: Fix idle S0ix ......................................................................
mb/google/brya: Fix idle S0ix
Change list: 1) Re-Enable dynamic GPIO PM 2) Select CR50_USE_LONG_INTERRUPT_PULSES to avoid CR50 IRQ short pulse issue
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 2 files changed, 1 insertion(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/56926/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9279f4b..e398fd2 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -11,6 +11,7 @@ config BOARD_GOOGLE_BRYA_COMMON def_bool y select BOARD_ROMSIZE_KB_32768 + select CR50_USE_LONG_INTERRUPT_PULSES select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 8a779bc..71967af 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -22,17 +22,6 @@ # Enable heci communication register "HeciEnabled" = "1"
- # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Enable CNVi BT register "CnviBtCore" = "true"