Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61777 )
Change subject: soc/amd/common/block/include/espi: rename IO/MMIO base/size registers ......................................................................
soc/amd/common/block/include/espi: rename IO/MMIO base/size registers
This aligns the register names more with the PPR.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 --- M src/soc/amd/common/block/include/amdblocks/espi.h 1 file changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/61777/1
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 4e8b898..cfba50b 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -15,20 +15,20 @@ #define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0)
-#define ESPI_IO_BASE_OFFSET_REG0 0x44 -#define ESPI_IO_BASE_OFFSET_REG1 0x48 -#define ESPI_IO_RANGE_SIZE_OFFSET 0x4c -#define ESPI_MMIO_BASE_OFFSET_REG0 0x50 -#define ESPI_MMIO_BASE_OFFSET_REG1 0x54 -#define ESPI_MMIO_BASE_OFFSET_REG2 0x58 -#define ESPI_MMIO_BASE_OFFSET_REG3 0x5c -#define ESPI_MMIO_OFFSET_SIZE_REG0 0x60 -#define ESPI_MMIO_OFFSET_SIZE_REG1 0x64 +#define ESPI_IO_BASE_REG0 0x44 +#define ESPI_IO_BASE_REG1 0x48 +#define ESPI_IO_SIZE0 0x4c +#define ESPI_MMIO_BASE_REG0 0x50 +#define ESPI_MMIO_BASE_REG1 0x54 +#define ESPI_MMIO_BASE_REG2 0x58 +#define ESPI_MMIO_BASE_REG3 0x5c +#define ESPI_MMIO_SIZE_REG0 0x60 +#define ESPI_MMIO_SIZE_REG1 0x64
-#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_OFFSET_REG0 + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_RANGE_SIZE_OFFSET + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_OFFSET_REG0 + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_OFFSET_SIZE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_SIZE0 + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_REG0 + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_SIZE_REG0 + ((range) & 3) * 2)
#define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100