Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41690 )
Change subject: mb/ocp/deltalake: Config PCH PCIe ports ......................................................................
mb/ocp/deltalake: Config PCH PCIe ports
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang Morgan_Jang@wiwynn.com --- M src/mainboard/ocp/deltalake/romstage.c 1 file changed, 12 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41690/1
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index c456913..f6b828f 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -22,24 +22,28 @@
static void mainboard_config_iio(FSPM_UPD *mupd) { + int index;
mupd->FspmConfig.IIoBifurcationTablePtr = (uint32_t) dl_iio_bifur_table; mupd->FspmConfig.NumOfIIoBifurcationTable = ARRAY_SIZE(dl_iio_bifur_table); + #if 0 mupd->FspmConfig.IioPciConfig.ConfigurationTable = (UPD_PCI_PORT_CONFIG *) dl_iio_pci_port; mupd->FspmConfig.IioPciConfig.NumberOfEntries = ARRAY_SIZE(dl_iio_pci_port); - - mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *) dl_pch_pci_port; - mupd->FspmConfig.PchPciConfig.NumberOfEntries = - ARRAY_SIZE(dl_pch_pci_port); - - mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; - mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; #endif + + for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { + mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = + dl_pch_pci_port[index].ForceEnable; + mupd->FspmConfig.PchPciePortLinkSpeed[dl_pch_pci_port[index].PortIndex] = + dl_pch_pci_port[index].PortLinkSpeed; + } + + mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00; + mupd->FspmConfig.PchPciePllSsc = 0xFE; }
void mainboard_memory_init_params(FSPM_UPD *mupd)