Attention is currently required from: Michał Kopeć.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68712 )
Change subject: mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily ......................................................................
mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily
Alder Lake FSP has bugged GPIO definitions for DEVSLP pins 6 and 7 which would cause incorrect programming of those pins when GpioOverride is disabled. Debug FSP will simply assert on DEVSLP programming.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I8b809851cefa339d172b95803aa8f49b441eddba --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 34 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/68712/1
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 189faf6..4485db7 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -14,19 +14,19 @@
# USB Configuration register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # USB-C LAN_USB1 - register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # MSI MYSTIC LIGHT - register "usb2_ports[2]" = "USB2_PORT_MAX(OC0)" # USB-A LAN_USB1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # JUSB5 - register "usb2_ports[4]" = "USB2_PORT_MAX(OC3)" # HUB to rear USB 2.0 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 - register "usb2_ports[10]" = "USB2_PORT_MAX(OC0)" # PS2_USB1 - register "usb2_ports[11]" = "USB2_PORT_MAX(OC0)" # PS2_USB1 - register "usb2_ports[12]" = "USB2_PORT_MAX(OC0)" # HUB to USB 2.0 headers - register "usb2_ports[13]" = "USB2_PORT_MAX(OC6)" # CNVi BT + register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers + register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 @@ -58,16 +58,18 @@ [7] = 1, }"
- register "sata_ports_dev_slp" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - [3] = 0, - [4] = 0, - [5] = 0, - [6] = 1, - [7] = 1, - }" + #FIXME: FSP has bugged definitions for DEVSLP pins 6 and 7. + #Enable the pins back when it is fixed or GpioOverride can be enabled. + #register "sata_ports_dev_slp" = "{ + # [0] = 0, + # [1] = 0, + # [2] = 0, + # [3] = 0, + # [4] = 0, + # [5] = 0, + # [6] = 1, + # [7] = 1, + #}"
# HDMI on port B register "ddi_portB_config" = "1"