Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22785
Change subject: stoneyridge/hudson: Replace "\t" from name table ......................................................................
stoneyridge/hudson: Replace "\t" from name table
Arrays intr_types[] (hudson) and its replacement irq_association[] (stoneyridge) use "\t" (tab) to force alignment when printing. As the checkpatch.pl program expands "\t" when testing, it can cause a "more than 80 characters" error when committing, while the actual line is less than 80 characters.
Replacing "\t" with the appropriate number of white spaces will have the double benefit of avoiding the "more than 80 characters" error and creating an alignment within the strings declarations.
BUG=b:70344551 TEST=stoneyridge: Build and boot, record output of irq routing and verify alignment. hudson: None (no board to test).
Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/pi/hudson/amd_pci_int_types.h 2 files changed, 56 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/22785/1
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index f8e06b3..d27f503 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -40,46 +40,46 @@ * Order is not important. */ const static struct irq_idx_name irq_association[] = { - { PIRQ_A, "INTA#\t" }, - { PIRQ_B, "INTB#\t" }, - { PIRQ_C, "INTC#\t" }, - { PIRQ_D, "INTD#\t" }, - { PIRQ_E, "INTE#\t" }, - { PIRQ_F, "INTF#\t" }, - { PIRQ_G, "INTG#\t" }, - { PIRQ_H, "INTH#\t" }, - { PIRQ_MISC, "Misc\t" }, - { PIRQ_MISC0, "Misc0\t" }, - { PIRQ_MISC1, "Misc1\t" }, - { PIRQ_MISC2, "Misc2\t" }, + { PIRQ_A, "INTA# " }, + { PIRQ_B, "INTB# " }, + { PIRQ_C, "INTC# " }, + { PIRQ_D, "INTD# " }, + { PIRQ_E, "INTE# " }, + { PIRQ_F, "INTF# " }, + { PIRQ_G, "INTG# " }, + { PIRQ_H, "INTH# " }, + { PIRQ_MISC, "Misc " }, + { PIRQ_MISC0, "Misc0 " }, + { PIRQ_MISC1, "Misc1 " }, + { PIRQ_MISC2, "Misc2 " }, { PIRQ_SIRQA, "Ser IRQ INTA" }, { PIRQ_SIRQB, "Ser IRQ INTB" }, { PIRQ_SIRQC, "Ser IRQ INTC" }, { PIRQ_SIRQD, "Ser IRQ INTD" }, - { PIRQ_SCI, "SCI\t" }, - { PIRQ_SMBUS, "SMBUS\t" }, - { PIRQ_ASF, "ASF\t" }, - { PIRQ_HDA, "HDA\t" }, - { PIRQ_FC, "FC\t\t" }, - { PIRQ_PMON, "PerMon\t" }, - { PIRQ_SD, "SD\t\t" }, - { PIRQ_SDIO, "SDIO\t" }, - { PIRQ_IMC0, "IMC INT0\t" }, - { PIRQ_IMC1, "IMC INT1\t" }, - { PIRQ_IMC2, "IMC INT2\t" }, - { PIRQ_IMC3, "IMC INT3\t" }, - { PIRQ_IMC4, "IMC INT4\t" }, - { PIRQ_IMC5, "IMC INT5\t" }, - { PIRQ_EHCI, "EHCI\t" }, - { PIRQ_XHCI, "XHCI\t" }, - { PIRQ_SATA, "SATA\t" }, - { PIRQ_GPIO, "GPIO\t" }, - { PIRQ_I2C0, "I2C0\t" }, - { PIRQ_I2C1, "I2C1\t" }, - { PIRQ_I2C2, "I2C2\t" }, - { PIRQ_I2C3, "I2C3\t" }, - { PIRQ_UART0, "UART0\t" }, - { PIRQ_UART1, "UART1\t" }, + { PIRQ_SCI, "SCI " }, + { PIRQ_SMBUS, "SMBUS " }, + { PIRQ_ASF, "ASF " }, + { PIRQ_HDA, "HDA " }, + { PIRQ_FC, "FC " }, + { PIRQ_PMON, "PerMon " }, + { PIRQ_SD, "SD " }, + { PIRQ_SDIO, "SDIO " }, + { PIRQ_IMC0, "IMC INT0 " }, + { PIRQ_IMC1, "IMC INT1 " }, + { PIRQ_IMC2, "IMC INT2 " }, + { PIRQ_IMC3, "IMC INT3 " }, + { PIRQ_IMC4, "IMC INT4 " }, + { PIRQ_IMC5, "IMC INT5 " }, + { PIRQ_EHCI, "EHCI " }, + { PIRQ_XHCI, "XHCI " }, + { PIRQ_SATA, "SATA " }, + { PIRQ_GPIO, "GPIO " }, + { PIRQ_I2C0, "I2C0 " }, + { PIRQ_I2C1, "I2C1 " }, + { PIRQ_I2C2, "I2C2 " }, + { PIRQ_I2C3, "I2C3 " }, + { PIRQ_UART0, "UART0 " }, + { PIRQ_UART1, "UART1 " }, };
/* diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index f898907..b90dc4d 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -17,23 +17,29 @@ #define AMD_PCI_INT_TYPES_H
const char * intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x7F] = "RSVD\t", + [0x00] = "INTA# ", "INTB# ", "INTC# ", "INTD# ", + "INTE# ", "INTF# ", "INTG# ", "INTH# ", + [0x08] = "Misc ", "Misc0 ", "Misc1 ", "Misc2 ", + "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI ", "SMBUS0 ", "ASF ", "HDA ", + "FC ", "GEC ", "PerMon ", "SD ", + [0x20] = "IMC INT0 ", "IMC INT1 ", "IMC INT2 ", "IMC INT3 ", + "IMC INT4 ", "IMC INT5 ", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", + "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x7F] = "RSVD ", #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) - [0x40] = "RSVD\t", "SATA\t", - [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", + [0x40] = "RSVD ", "SATA ", + [0x60] = "RSVD ", "RSVD ", "GPIO ", #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", + [0x40] = "IDE ", "SATA ", + [0x50] = "GPPInt0 ", "GPPInt1 ", "GPPInt2 ", "GPPInt3 ", #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", - [0x62] = "GPIO\t", - [0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t", + [0x40] = "IDE ", "SATA ", + [0x50] = "GPPInt0 ", "GPPInt1 ", "GPPInt2 ", "GPPInt3 ", + [0x62] = "GPIO ", + [0x70] = "I2C0 ", "I2C1 ", "I2C2 ", "I2C3 ", + "UART0 ", "UART1 ", #endif };