Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35446 )
Change subject: mb/google/hatch/variants/helios: Update DPTF parameters ......................................................................
mb/google/hatch/variants/helios: Update DPTF parameters
Update DPTF thermal temperature threshold values for CML based Helios system.
BUG=141087272 BRANCH=None TEST=Build and Boot on Helios board.
Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl 1 file changed, 20 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35446/1
diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index 30dcf13..9aa3928 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -15,21 +15,33 @@
#define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 105 -#define DPTF_CPU_ACTIVE_AC0 55 -#define DPTF_CPU_ACTIVE_AC1 50 -#define DPTF_CPU_ACTIVE_AC2 45 -#define DPTF_CPU_ACTIVE_AC3 30 -#define DPTF_CPU_ACTIVE_AC4 20 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75
#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 0 -#define DPTF_TSR0_CRITICAL 0 +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 40 +#define DPTF_TSR0_ACTIVE_AC5 38
#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 45 -#define DPTF_TSR1_CRITICAL 0 +#define DPTF_TSR1_CRITICAL 65 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 40 +#define DPTF_TSR1_ACTIVE_AC5 38
#define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL