[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures

[Angel Pons (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Sowmya Aralguppe, Subrata Banik, Tarun.

Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email )

Change subject: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures
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Patch Set 19:

(2 comments)

File src/soc/intel/common/block/crashlog/crashlog.c:

https://review.coreboot.org/c/coreboot/+/83106/comment/bfbac6a1_b7fa5ad4?usp... :
PS19, Line 318: 		/* DW by DW copy: byte access to PMC SRAM not allowed */
Try adding this, then build for x86_64:

```suggestion
    	/* DW by DW copy: byte access to PMC SRAM not allowed */
    	_Static_assert(sizeof(u32) == sizeof(uintptr_t), "this is not a DW by DW copy");
```

This will error out. So you have to apply the suggestion below (and remove the assertion).

https://review.coreboot.org/c/coreboot/+/83106/comment/41544e65_38c3ab33?usp... :
PS19, Line 321: 		src_addr += sizeof(uintptr_t);
On 64-bit builds, this can't possibly work. `read32p()` always reads 4 bytes, but the address gets incremented by `sizeof(uintptr_t)`, which is 4 bytes on 32-bit builds but 8 bytes on 64-bit builds.

Please change:

```suggestion
    	src_addr += sizeof(u32);
```