[coreboot-gerrit] Change in coreboot[master]: mb/google/nissa/var/nivviks: Add GL9750 power sequence

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Reka Norman, Eric Lai.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62722 )

Change subject: mb/google/nissa/var/nivviks: Add GL9750 power sequence
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Patch Set 1:

(1 comment)

File src/mainboard/google/brya/variants/nivviks/gpio.c:

https://review.coreboot.org/c/coreboot/+/62722/comment/83802413_88d38a62 
PS1, Line 56: PAD_CFG_GPO(GPP_H12, 1, DEEP)
> If it works in ramstage too, it seems simpler to just do it there. […]

If you check brya variants again, you will see several of them have moved deassertoin of PERST_L for storage devices to romstage GPIO table. There appears to be some timing change in ADL FSP where it is scanning PCIe RPs for downstream devices earlier than prior FSPs.