mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31450 )
Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop ......................................................................
Patch Set 4:
Patch Set 4:
Patch Set 3:
here is a correct datasheet for G505S - LA-A091P motherboard - http://www.s-manuals.com/pdf/motherboard/compal/compal_la-a091p_r1.0_schemat... . I don't know how to find a correct GPIO there... but it is not necessary anymore: see comment above, it turned out we could set BottomIO to 0xD0 for all G505S
Page 36 middle-right BRDID and it's 4-state analog input Vab on KB9012 embedded controller. Maybe something you can find from ACPI / EC commands.
OT: Have you poked on EC_TX and EC_RX signals? I *think* you would need some 10k or so pull-up, see comment on page 30.
Kyosti, thank you for your discoveries. Although recently we found out that we could just set it to BottomIO to 0xD0 for all G505S regardless of them having a discrete GPU (so no need to distinguish between them at the moment), maybe this information could be useful sometime in the future.
Could you please describe in more detail what exactly these EC_TX and EC_RX signals may be useful for? If for debug card - I already got it and tried inserting to this miniPCIe slot, and it is fully working: displaying the POST codes properly. More information at http://dangerousprototypes.com/docs/Compal_POST_diagnostic_card . This Compal datasheet is a bit older than motherboard and maybe these pull-ups have been implemented to the motherboard. Also, I hope that everything I am doing will be available to G505S people without requiring them to do any motherboard soldering, it could be risky for some.
Sorry, I just discovered that my patch above does not choose these configurations but I am using them in my local .config :
CONFIG_PCIEXP_L1_SUB_STATE=y #Enable PCIe Common Clock CONFIG_PCIEXP_ASPM=y #Enable PCIe ASPM CONFIG_PCIEXP_COMMON_CLOCK=y #Enable PCIe Clock Power Management CONFIG_PCIEXP_CLK_PM=y #Enable PCIe ASPM L1 SubState
Soon I will submit a new revision of this patch which will select these .config options for G505S by default.