Attention is currently required from: David Wu, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee.
Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56539 )
Change subject: mb/google/brya: Enable DDR4 SODIMM for brask
......................................................................
Patch Set 16:
(2 comments)
File src/mainboard/google/brya/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/56539/comment/bf7ae98b_4f9e5445
PS15, Line 24: RW_SPD_CACHE(PRESERVE) 4K
Can you add a comment here, e.g.: […]
Ack
File src/mainboard/google/brya/variants/baseboard/brask/memory.c:
https://review.coreboot.org/c/coreboot/+/56539/comment/a4c9ebf6_2a4ca7ce
PS15, Line 38: variant_get_spd_info
This should be called in `romstage.c now, e.g.: […]
We do have called this function in romstage.c.
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