[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 )

Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
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Patch Set 23:

(2 comments)

File src/mainboard/intel/mtlrvp/romstage.c:

https://review.coreboot.org/c/coreboot/+/66190/comment/0f165318_f2b93646 
PS23, Line 41: 		die("Unknown board id = 0x%x\n", board_id);
> @Subrata, here.

better we die here, otherwise FSP-M might hang (for sure) and it would be hard debugging that w/o the debug FSP log

File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c:

https://review.coreboot.org/c/coreboot/+/66190/comment/b7a73244_029eaf7d 
PS23, Line 35: 		die("Unknown board id = 0x%x\n", board_id);
> @Subrata, here too.

same