build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44699 )
Change subject: soc/mediatek/mt8192: Add dram control register define and bits define ......................................................................
Patch Set 1:
(33 comments)
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... File src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 121: { open brace '{' following enum go on the same line
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 122: SINGLE_RANK_DDR = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 123: DUAL_RANK_DDR please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 258: void after_calib(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 274: void dramc_write_leveling(const struct ddr_cali* cali, u8 dqs_final_delay[2][2]); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 275: void dramc_rx_dqs_gating_cal(const struct ddr_cali* cali, u8 *txdly_min, u8 *txdly_max); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 276: void dramc_rx_dqs_gating_post_process(const struct ddr_cali* cali, "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 278: void dramc_rx_datlat_cal(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 279: void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 280: void dramc_cmd_bus_training(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 281: void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type type); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 282: void dramc_tx_window_perbit_cal(const struct ddr_cali* cali, tx_cali_type calType, "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 284: void dramc_tx_oe_calibration(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 300: void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu); line over 96 characters
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 312: void dramc_dqs_precalculation_preset(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 314: void dramc_hmr4_presetting(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 317: void dramc_cke_debounce(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 318: void dramc_hw_dqsosc(const struct ddr_cali* cali, u8 chn); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 319: void xrtwtw_shu_setting(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 320: void enable_write_DBI_after_calibration(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 321: void dramc_set_mr13_vrcg_to_normal(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 329: void ana_clk_div_config( ana_dvfs_core *tr,dvfs_group_config *dfs); space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 329: void ana_clk_div_config( ana_dvfs_core *tr,dvfs_group_config *dfs); space prohibited after that open parenthesis '('
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 334: void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali* cali, "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 336: void dqsosc_shu_settings(const struct ddr_cali* cali, "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 338: void shift_dq_ui(const struct ddr_cali* cali, u8 rk, s8 shift_ui); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 339: void shuffle_dfs_to_fsp1(const struct ddr_cali* cali); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 340: u8 get_cbt_vref_pinmux_value(const struct ddr_cali* cali, u8 range, u8 vref_lev); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 341: void o1_path_on_off(const struct ddr_cali* cali, o1_state o1); "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... File src/soc/mediatek/mt8192/include/soc/dramc_register.h:
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 3: #ifndef __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ exactly one space required after that #ifndef
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... File src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h:
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 3: #ifndef __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ exactly one space required after that #ifndef
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 759: DEFINE_BIT(MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 10) 'DIABLE' may be misspelled - perhaps 'DISABLE'?
https://review.coreboot.org/c/coreboot/+/44699/1/src/soc/mediatek/mt8192/inc... PS1, Line 2837: #endif //__SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ adding a line without newline at end of file