Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76040?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for gpio_override_pm dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for gpio_override_pm dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="gpio_override_pm" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: Ie4babb59ca833aead5ce137357090856b6fcf720 Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/76040/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index c83ce0c..0afc9fa 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -205,7 +205,7 @@ register "PcieClkSrcClkReq[2]" = "2"
# GPIO PM programming - register "gpio_override_pm" = "1" + register gpio_override_pm = true
# GPIO community PM configuration # Disable dynamic clock gating; with bits 0-5 set in these registers, diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cd5506d..5b59d78 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -184,7 +184,7 @@ register PchHdaAudioLinkDmic1 = false
# GPIO PM programming - register "gpio_override_pm" = "1" + register gpio_override_pm = true
# GPIO community PM configuration # Disable dynamic clock gating; with bits 0-5 set in these registers, diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index fee9707..8bc28d4 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -184,7 +184,7 @@ register PchHdaAudioLinkDmic1 = false
# GPIO PM programming - register "gpio_override_pm" = "1" + register gpio_override_pm = true
# GPIO community PM configuration # Disable dynamic clock gating; with bits 0-5 set in these registers, diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cde96fb..e2d289d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -199,7 +199,7 @@ register "PcieClkSrcClkReq[4]" = "4"
# GPIO PM programming - register "gpio_override_pm" = "1" + register gpio_override_pm = true
# GPIO community PM configuration register "gpio_pm[COMM_0]" = "MISCCFG_GPIO_PM_CONFIG_BITS" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f5a2b17..240fd70 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -204,7 +204,7 @@ register "PcieClkSrcClkReq[2]" = "2"
# GPIO PM programming - register "gpio_override_pm" = "1" + register gpio_override_pm = true
# GPIO community PM configuration register "gpio_pm[COMM_0]" = "MISCCFG_GPIO_PM_CONFIG_BITS"