Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29330
Change subject: src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines ......................................................................
src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines
The GPIO and ACPI base sizes have defines, but they are not used. Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.
BUG=N/A TEST=Intel BayTrail CRB
Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/intel/baytrail/southcluster.c 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29330/1
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 0ef70d0..f44f502 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -107,10 +108,10 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIO */ - sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); + sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE);
/* ACPI */ - sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); + sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); }
static void sc_read_resources(struct device *dev)