Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56595 )
Change subject: mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports ......................................................................
mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports
Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports.
Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-by: Paul Menzel paulepanter@mailbox.org --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index d1c5c82..f05f025 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -77,6 +77,14 @@ register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+ # Disable LTR for all PCIe root ports + register "PcieRpLtrDisable[0]" = "true" + register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[2]" = "true" + register "PcieRpLtrDisable[3]" = "true" + register "PcieRpLtrDisable[4]" = "true" + register "PcieRpLtrDisable[5]" = "true" + # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1"