Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50828 )
Change subject: mb/google/volteer: Fix FPMCU pwr/rst gpio handling ......................................................................
mb/google/volteer: Fix FPMCU pwr/rst gpio handling
1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5
On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2.
This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel
BUG=b:178094376 TEST=none
Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/smihandler.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/drobit/Makefile.inc M src/mainboard/google/volteer/variants/drobit/gpio.c A src/mainboard/google/volteer/variants/drobit/ramstage.c M src/mainboard/google/volteer/variants/eldrid/Makefile.inc M src/mainboard/google/volteer/variants/eldrid/gpio.c A src/mainboard/google/volteer/variants/eldrid/ramstage.c M src/mainboard/google/volteer/variants/elemi/Makefile.inc M src/mainboard/google/volteer/variants/elemi/gpio.c A src/mainboard/google/volteer/variants/elemi/ramstage.c M src/mainboard/google/volteer/variants/halvor/Makefile.inc M src/mainboard/google/volteer/variants/halvor/gpio.c A src/mainboard/google/volteer/variants/halvor/ramstage.c M src/mainboard/google/volteer/variants/malefor/Makefile.inc M src/mainboard/google/volteer/variants/malefor/gpio.c A src/mainboard/google/volteer/variants/malefor/ramstage.c M src/mainboard/google/volteer/variants/terrador/Makefile.inc M src/mainboard/google/volteer/variants/terrador/gpio.c A src/mainboard/google/volteer/variants/terrador/ramstage.c M src/mainboard/google/volteer/variants/trondo/Makefile.inc M src/mainboard/google/volteer/variants/trondo/gpio.c A src/mainboard/google/volteer/variants/trondo/ramstage.c M src/mainboard/google/volteer/variants/voema/Makefile.inc M src/mainboard/google/volteer/variants/voema/gpio.c A src/mainboard/google/volteer/variants/voema/ramstage.c M src/mainboard/google/volteer/variants/volteer2/Makefile.inc M src/mainboard/google/volteer/variants/volteer2/gpio.c A src/mainboard/google/volteer/variants/volteer2/ramstage.c M src/mainboard/google/volteer/variants/voxel/Makefile.inc M src/mainboard/google/volteer/variants/voxel/gpio.c A src/mainboard/google/volteer/variants/voxel/ramstage.c 33 files changed, 395 insertions(+), 36 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c index adb60fe..7a02825 100644 --- a/src/mainboard/google/volteer/smihandler.c +++ b/src/mainboard/google/volteer/smihandler.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <baseboard/variants.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> @@ -14,6 +15,12 @@
void mainboard_smi_sleep(u8 slp_typ) { + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(slp_typ, &num); + gpio_configure_pads(pads, num); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 5ae3a02..f1df09e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -451,6 +451,13 @@ return early_gpio_table; }
+const struct pad_config *__weak variant_sleep_gpio_table(u8 slp_typ, + size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 3d12c85..685440c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -14,6 +14,7 @@ */ const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/volteer/variants/drobit/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/Makefile.inc index 343c7db..3454eec 100644 --- a/src/mainboard/google/volteer/variants/drobit/Makefile.inc +++ b/src/mainboard/google/volteer/variants/drobit/Makefile.inc @@ -5,3 +5,4 @@ bootblock-y += gpio.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/drobit/gpio.c b/src/mainboard/google/volteer/variants/drobit/gpio.c index 8feadff..b0496af 100644 --- a/src/mainboard/google/volteer/variants/drobit/gpio.c +++ b/src/mainboard/google/volteer/variants/drobit/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -18,8 +19,6 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ @@ -57,8 +56,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), @@ -179,3 +176,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/drobit/ramstage.c b/src/mainboard/google/volteer/variants/drobit/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/eldrid/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc index 343c7db..3454eec 100644 --- a/src/mainboard/google/volteer/variants/eldrid/Makefile.inc +++ b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc @@ -5,3 +5,4 @@ bootblock-y += gpio.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 6810ba5..8712f9c 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -18,8 +19,6 @@ PAD_NC(GPP_A15, NONE), /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
@@ -59,8 +58,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */ PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), @@ -219,3 +216,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/eldrid/ramstage.c b/src/mainboard/google/volteer/variants/eldrid/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc index b0bfc56..3488dc6 100644 --- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c index bbdb517..061aaec 100644 --- a/src/mainboard/google/volteer/variants/elemi/gpio.c +++ b/src/mainboard/google/volteer/variants/elemi/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -18,8 +19,6 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ @@ -71,8 +70,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), @@ -232,3 +229,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/elemi/ramstage.c b/src/mainboard/google/volteer/variants/elemi/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index b0bfc56..3488dc6 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index c98003b..7d6725a 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -35,8 +36,6 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), /* A23 : I2S1_SCLK ==> HP_INT_L */ @@ -79,8 +78,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), @@ -245,3 +242,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/halvor/ramstage.c b/src/mainboard/google/volteer/variants/halvor/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/malefor/Makefile.inc b/src/mainboard/google/volteer/variants/malefor/Makefile.inc index 343c7db..3454eec 100644 --- a/src/mainboard/google/volteer/variants/malefor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/malefor/Makefile.inc @@ -5,3 +5,4 @@ bootblock-y += gpio.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index 3a98081..af78eff 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -31,8 +32,6 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ @@ -75,8 +74,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), @@ -208,3 +205,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/malefor/ramstage.c b/src/mainboard/google/volteer/variants/malefor/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/malefor/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/terrador/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/Makefile.inc index b0bfc56..3488dc6 100644 --- a/src/mainboard/google/volteer/variants/terrador/Makefile.inc +++ b/src/mainboard/google/volteer/variants/terrador/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index 80e1b96..66bc15b 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -20,8 +21,6 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
@@ -70,8 +69,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), @@ -232,3 +229,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/terrador/ramstage.c b/src/mainboard/google/volteer/variants/terrador/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/trondo/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/Makefile.inc index 13269db..6c5454f 100644 --- a/src/mainboard/google/volteer/variants/trondo/Makefile.inc +++ b/src/mainboard/google/volteer/variants/trondo/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/trondo/gpio.c b/src/mainboard/google/volteer/variants/trondo/gpio.c index 11b051b..988f95a 100644 --- a/src/mainboard/google/volteer/variants/trondo/gpio.c +++ b/src/mainboard/google/volteer/variants/trondo/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -37,3 +38,19 @@ *num = ARRAY_SIZE(cros_gpios); return cros_gpios; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/trondo/ramstage.c b/src/mainboard/google/volteer/variants/trondo/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/voema/Makefile.inc b/src/mainboard/google/volteer/variants/voema/Makefile.inc index b0bfc56..3488dc6 100644 --- a/src/mainboard/google/volteer/variants/voema/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c index da85260..8e59e1c 100644 --- a/src/mainboard/google/volteer/variants/voema/gpio.c +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -22,8 +23,6 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
@@ -72,8 +71,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), @@ -228,3 +225,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/voema/ramstage.c b/src/mainboard/google/volteer/variants/voema/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc index 04af3ae..fcf70cb 100644 --- a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc @@ -3,4 +3,5 @@ bootblock-y += gpio.c
ramstage-y += gpio.c +ramstage-y += ramstage.c ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 262c016..588aa17 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -22,8 +23,6 @@ PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ PAD_NC(GPP_A20, NONE), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ @@ -73,8 +72,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), @@ -271,3 +268,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/volteer2/ramstage.c b/src/mainboard/google/volteer/variants/volteer2/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index b0bfc56..3488dc6 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += memory.c
ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index 6be86de..4ec02c5 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -18,8 +19,6 @@ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ @@ -80,8 +79,6 @@ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), @@ -279,3 +276,19 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/voxel/ramstage.c b/src/mainboard/google/volteer/variants/voxel/ramstage.c new file mode 100644 index 0000000..b198992 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +}