Shaunak Saha (shaunak.saha@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17211
-gerrit
commit 66b7220e0e45510b7a70bfb2dd6eadf504266343 Author: Shaunak Saha shaunak.saha@intel.com Date: Wed Nov 2 10:52:23 2016 -0700
soc/intel: Add MSR to support enabling turbo frequency
This patch adds definition for IA32_PERF_CTL and FREQ_LIMIT_RATIO MSR's. FREQ_LIMIT_RATIO register allows determines the ratio limits to be used to limit frequency. PERF_CTL is Performance Control MSR. BIOS makes request for a new Performance state (P-state) by writing this MSR.
BUG=chrome-os-partner:58158 BRANCH=None
Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- src/include/cpu/intel/turbo.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 6626cb1..36c8eab 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -23,9 +23,13 @@ #define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 +#define APL_BURST_MODE_DISABLE 0x0000004000000000ULL
#define H_MISC_DISABLE_TURBO (1 << 6)
+#define IA32_PERL_CTL 0x199 +#define FREQ_LIMIT_RATIO 0x1AD + enum { TURBO_UNKNOWN, TURBO_UNAVAILABLE,