4 Nov
2020
4 Nov
'20
10:30 p.m.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46761 )
Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... File src/soc/intel/broadwell/pch/acpi/pcie_port.asl:
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... PS10, Line 11: 5A nit, 0x5a?
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... PS10, Line 14: DF nit, 0xdf
Actually, `Offset (0xdc), , 30,` would be much nicer.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c
Gerrit-Change-Number: 46761
Gerrit-PatchSet: 10
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu
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