[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor

[Ziang Wang (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu.

Ziang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email )

Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
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Patch Set 7:

(1 comment)

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/75740/comment/2bb3b18c_94c02a5c :
PS1, Line 277: 	 * Persistent Memory 300 Series mapped as memory) per Socket
> Thanks. So 3DS isn't part of the calculation, I guess. Can one have max. DRAM
> and max. Optane at once? If not, isn't it like `MAX(MAX_DRAM, MAX_OPTANE)`?
> So 4GiB?

Yes, one can have both (so 6TB), it is clarified in SPR spec.
> Then give it a meaning macro name instead 6 would be better. Like max_support_unit or something.

Done.