Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/55f9f8b1_1a82f9ca
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
What if we aggregate both operations covered by SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOT […]
Hmm, I mean remove SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT & SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE, and bring entire code (covered by these 2 flags) under CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH.
From SoC recommendation side, Ready to Boot and End of Post are event which has meaning and silicon prefer to perform some operation under specific hoods, hence, coreboot would allow the same flexibility for SoC vendor enggs to add the required code inside specific `if` clause without mixing it.
From the code perspective, both the flags are getting executed sequentially and not as two disjoint events.
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