[coreboot-gerrit] [S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email )

Change subject: ec/google/chromeec: Add indexed IO support
......................................................................

ec/google/chromeec: Add indexed IO support

Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.

BUG=b:379224648
TEST= able to build nissa/trulo.

Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85449
Tested-by: build bot (Jenkins) 
Reviewed-by: Caveh Jalali 
Reviewed-by: Subrata Banik 
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/ec_lpc.c
2 files changed, 41 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Caveh Jalali: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index eae1fc6..cf3dc9f 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -60,6 +60,30 @@
      this option simply enables the LPC EC code.  The eSPI device
      still needs to correctly configure the bus transactions.

+config EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO
+	depends on EC_GOOGLE_CHROMEEC && ARCH_X86
+	def_bool n
+	help
+	  Google Chrome EC enable support for indexed I/O access.
+
+	  Indexed I/O allows devices with multiple memory locations to be
+	  accessed using a single I/O port base address and an index register.
+	  A separate data register, typically located at the address
+	  immediately following the index register, is used for sending and
+	  receiving data to the device.
+
+	  Ensure port address and gen3_dec values are correct when selecting
+	  this configuration.
+
+config EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PORT
+	depends on EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO
+	hex
+	default 0x380
+	help
+	  Google Chrome EC indexed I/O access address.
+
+	  Index register port address for memory mapped indexed IO access
+
 config EC_GOOGLE_CHROMEEC_LPC
    depends on ARCH_X86  # Needs Plug-and-play.
    def_bool n
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 2a9eabb..e661cf5 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -52,6 +52,15 @@
    return byte;
 }

+#if CONFIG(EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO)
+/* Read singe byte and return byte read using indexed IO*/
+static inline u8 read_byte_indexed_io(u8 offset)
+{
+	outb(offset, CONFIG_EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PORT);
+	return inb(CONFIG_EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PORT + 1);
+}
+#endif
+
 /*
  * Write bytes to a given LPC-mapped address.
  *
@@ -156,6 +165,10 @@
    	printk(BIOS_ERR, "Error reading memmap data.\n");
    	return -1;
    }
+#elif CONFIG(EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO)
+	id1 = read_byte_indexed_io(EC_MEMMAP_ID);
+	id2 = read_byte_indexed_io(EC_MEMMAP_ID + 1);
+	flags = read_byte_indexed_io(EC_MEMMAP_HOST_CMD_FLAGS);
 #else
    id1 = read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID);
    id2 = read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1);
@@ -358,7 +371,11 @@
 /* Return the byte of EC switch states */
 uint8_t google_chromeec_get_switches(void)
 {
+#if CONFIG(EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO)
+	return read_byte_indexed_io(EC_MEMMAP_SWITCHES);
+#else
    return read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+#endif
 }

void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size)