Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10401
-gerrit
commit bca178dbb7f2e026363cf3a5931d01c918f7921a Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Tue Jun 2 13:47:36 2015 -0500
cpu/amd: Detect any conflicts betwwen sysinfo and the stack region
When increasing the number of supported CPUs on AMD Family 10h/15h systems there is a relatively high chance of causing a collision between the CAR global variable region and the AP stack space.
Detect collision at runtime and print a warning if collision is present.
Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/cpu/Kconfig | 6 ++++++ src/cpu/amd/car/cache_as_ram.inc | 3 ++- src/cpu/amd/model_10xxx/Kconfig | 8 ++++++++ src/cpu/amd/model_10xxx/init_cpus.c | 7 +++++++ 4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c8dc136..ae2e88c 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,12 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex
+config DCACHE_BSP_STACK_SIZE + hex + +config DCACHE_AP_STACK_SIZE + hex + config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..1c22447 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -24,9 +24,10 @@
#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE
/* For CAR with Fam10h. */ -#define CacheSizeAPStack 0x400 /* 1K */ +#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE
#define MSR_MCFG_BASE 0xC0010058 #define MSR_FAM10 0xC001102A diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index cd69cae..4b5cded 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -30,6 +30,14 @@ config DCACHE_RAM_SIZE hex default 0x0c000
+config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + config UDELAY_IO bool default n diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 62ba0b0..aa21f37 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -250,6 +250,13 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) u32 apicid; struct node_core_id id;
+ void * lower_stack_region_boundary = (void*)((CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2)) + - (CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE)); + if (((void*)(sysinfo+1)) > lower_stack_region_boundary) + printk(BIOS_WARNING, + "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", + sysinfo, sysinfo + 1, lower_stack_region_boundary); + /* * already set early mtrr in cache_as_ram.inc */