[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Use updated name for sbadaddr

[Arthur Heymans (Code Review)]

Attention is currently required from: Philipp Hug, Arthur Heymans, ron minnich.
Hello Arthur Heymans,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/63073

to review the following change.

Change subject: arch/riscv: Use updated name for sbadaddr
......................................................................

arch/riscv: Use updated name for sbadaddr

The riscv spec v1.10.0 updated this name.
This fixes building with clang.

Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532
Signed-off-by: Arthur Heymans 
---
M src/arch/riscv/trap_handler.c
M src/arch/riscv/trap_util.S
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/63073/1

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index f940f63..a3aad48 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -150,7 +150,7 @@
 /* This function used to redirect trap to s-mode. */
 void redirect_trap(void)
 {
-	write_csr(sbadaddr, read_csr(mbadaddr));
+	write_csr(mtval, read_csr(mtval));
    write_csr(sepc, read_csr(mepc));
    write_csr(scause, read_csr(mcause));
    write_csr(mepc, read_csr(stvec));
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index f1c4c4d..c106d5b 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -80,7 +80,7 @@
   csrrw  t0,mscratch,x0
   csrr   s0,mstatus
   csrr   t1,mepc
-  csrr   t2,mbadaddr
+  csrr   t2,mtval
   csrr   t3,mcause
   STORE  t0,2*REGBYTES(x2)
   STORE  s0,32*REGBYTES(x2)