Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu.
Hello Yidi Lin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/84026?usp=email
to review the following change.
Change subject: soc/mediatek/mt8196: Add EINT support ......................................................................
soc/mediatek/mt8196: Add EINT support
BUG=b:334723688 TEST=EINT works in Rauru
Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Signed-off-by: Yidi Lin yidilin@chromium.org --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/eint.c 2 files changed, 118 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84026/1
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 5070e8d..a1c742d 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -3,7 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y)
all-y += ../common/flash_controller.c -all-y += ../common/gpio.c ../common/gpio_op.c gpio.c +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c eint.c all-y += ../common/i2c.c i2c.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += ../common/snfc.c diff --git a/src/soc/mediatek/mt8196/eint.c b/src/soc/mediatek/mt8196/eint.c new file mode 100644 index 0000000..8069f42 --- /dev/null +++ b/src/soc/mediatek/mt8196/eint.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196_EINT_Datasheet + * Chapter number: 1 + */ + +#include <soc/addressmap.h> +#include <soc/gpio_common.h> + +static uint32_t eint_data[][4] = { + /* {eint_num, instance, index, debounce} */ + {0, 2, 0, 1}, {1, 2, 1, 1}, {2, 2, 16, 0}, {3, 2, 17, 0}, + {4, 2, 2, 1}, {5, 2, 3, 1}, {6, 2, 4, 1}, {7, 2, 5, 1}, + {8, 2, 6, 1}, {9, 2, 18, 0}, {10, 2, 7, 1}, {11, 2, 8, 1}, + {12, 2, 9, 1}, {13, 1, 4, 0}, {14, 0, 0, 1}, {15, 1, 5, 0}, + {16, 1, 6, 0}, {17, 1, 7, 0}, {18, 1, 8, 0}, {19, 1, 9, 0}, + {20, 0, 1, 1}, {21, 0, 10, 0}, {22, 0, 11, 0}, {23, 0, 12, 0}, + {24, 0, 13, 0}, {25, 0, 14, 0}, {26, 0, 15, 0}, {27, 0, 2, 1}, + {28, 0, 16, 0}, {29, 0, 17, 0}, {30, 0, 18, 0}, {31, 0, 3, 1}, + {32, 0, 19, 0}, {33, 0, 20, 0}, {34, 0, 21, 0}, {35, 0, 22, 0}, + {36, 0, 23, 0}, {37, 0, 24, 0}, {38, 0, 25, 0}, {39, 2, 10, 1}, + {40, 2, 11, 1}, {41, 2, 12, 1}, {42, 2, 13, 1}, {43, 2, 14, 1}, + {44, 2, 19, 0}, {45, 2, 20, 0}, {46, 2, 21, 0}, {47, 2, 22, 0}, + {48, 2, 23, 0}, {49, 2, 24, 0}, {50, 2, 25, 0}, {51, 2, 26, 0}, + {60, 2, 27, 0}, {61, 2, 28, 0}, {62, 2, 29, 0}, {63, 2, 30, 0}, + {64, 2, 31, 0}, {65, 2, 32, 0}, {70, 2, 33, 0}, {71, 2, 34, 0}, + {72, 2, 35, 0}, {73, 2, 36, 0}, {74, 2, 37, 0}, {79, 2, 38, 0}, + {80, 2, 39, 0}, {81, 2, 40, 0}, {82, 2, 41, 0}, {83, 2, 42, 0}, + {84, 2, 43, 0}, {85, 2, 44, 0}, {86, 2, 45, 0}, {87, 2, 46, 0}, + {88, 2, 47, 0}, {89, 2, 48, 0}, {90, 2, 49, 0}, {91, 2, 50, 0}, + {92, 2, 15, 1}, {93, 2, 51, 0}, {94, 2, 52, 0}, {95, 2, 53, 0}, + {96, 2, 54, 0}, {97, 2, 55, 0}, {98, 2, 56, 0}, {103, 2, 57, 0}, + {106, 1, 10, 0}, {107, 1, 11, 0}, {108, 1, 12, 0}, {109, 1, 13, 0}, + {110, 1, 0, 1}, {111, 1, 1, 1}, {112, 1, 2, 1}, {113, 1, 3, 1}, + {114, 1, 14, 0}, {115, 1, 15, 0}, {116, 1, 16, 0}, {117, 1, 17, 0}, + {118, 1, 18, 0}, {119, 1, 19, 0}, {120, 1, 20, 0}, {121, 1, 21, 0}, + {122, 1, 22, 0}, {125, 1, 23, 0}, {126, 1, 24, 0}, {127, 1, 25, 0}, + {128, 1, 26, 0}, {129, 1, 27, 0}, {130, 1, 28, 0}, {137, 0, 26, 0}, + {138, 0, 27, 0}, {139, 0, 28, 0}, {140, 0, 29, 0}, {141, 0, 30, 0}, + {142, 0, 31, 0}, {143, 0, 32, 0}, {144, 0, 33, 0}, {145, 0, 34, 0}, + {146, 0, 35, 0}, {147, 0, 36, 0}, {148, 0, 4, 1}, {149, 0, 37, 0}, + {150, 0, 5, 1}, {151, 0, 38, 0}, {152, 0, 39, 0}, {153, 0, 40, 0}, + {154, 0, 41, 0}, {155, 0, 42, 0}, {156, 0, 43, 0}, {157, 0, 44, 0}, + {158, 0, 45, 0}, {159, 0, 46, 0}, {160, 0, 47, 0}, {161, 0, 48, 0}, + {162, 0, 49, 0}, {163, 0, 50, 0}, {164, 0, 51, 0}, {165, 0, 52, 0}, + {166, 0, 53, 0}, {167, 0, 54, 0}, {168, 0, 55, 0}, {169, 0, 56, 0}, + {170, 0, 57, 0}, {171, 0, 58, 0}, {172, 0, 6, 1}, {173, 0, 7, 1}, + {174, 0, 8, 1}, {175, 0, 9, 1}, {178, 0, 59, 0}, {179, 0, 60, 0}, + {180, 0, 61, 0}, {181, 0, 62, 0}, {182, 0, 63, 0}, {183, 0, 64, 0}, + {184, 0, 65, 0}, {185, 0, 66, 0}, {186, 3, 6, 0}, {187, 3, 7, 0}, + {192, 3, 8, 0}, {193, 3, 9, 0}, {196, 3, 10, 0}, {197, 3, 11, 0}, + {204, 3, 12, 0}, {205, 3, 13, 0}, {206, 3, 14, 0}, {207, 3, 0, 1}, + {208, 3, 1, 1}, {209, 3, 2, 1}, {210, 3, 15, 0}, {211, 3, 3, 1}, + {212, 3, 4, 1}, {213, 3, 5, 1}, {216, 3, 16, 0}, {217, 3, 17, 0}, + {218, 3, 18, 0}, {219, 3, 19, 0}, {220, 3, 20, 0}, {221, 3, 21, 0}, + {222, 3, 22, 0}, {223, 3, 23, 0}, {224, 3, 24, 0}, {225, 3, 25, 0}, + {226, 3, 26, 0}, {227, 3, 27, 0}, {228, 3, 28, 0}, {229, 3, 29, 0}, + {241, 3, 30, 0}, {242, 3, 31, 0}, {243, 3, 32, 0}, {245, 3, 45, 0}, + {251, 0, 67, 0}, {252, 0, 68, 0}, {253, 0, 69, 0}, {254, 0, 70, 0}, + {255, 0, 71, 0}, {256, 0, 72, 0}, {257, 0, 73, 0}, {258, 0, 74, 0}, + {259, 3, 33, 0}, {260, 3, 34, 0}, {261, 3, 35, 0}, {262, 3, 36, 0}, + {263, 3, 37, 0}, {264, 3, 38, 0}, {265, 3, 39, 0}, {266, 3, 40, 0}, + {267, 3, 41, 0}, {268, 3, 42, 0}, {269, 3, 43, 0}, {270, 3, 44, 0}, + {271, 4, 0, 0}, {272, 4, 1, 0}, {273, 4, 2, 0}, {274, 4, 3, 0}, + {275, 4, 4, 0}, {276, 4, 5, 0}, {277, 4, 6, 0}, {278, 4, 7, 0}, + {279, 4, 8, 0}, {280, 4, 9, 0}, {281, 4, 10, 0}, {282, 4, 11, 0}, + {283, 4, 12, 0}, {284, 4, 13, 0}, {285, 4, 14, 0}, {286, 4, 15, 0}, + {287, 4, 16, 0}, {288, 4, 17, 0}, {289, 4, 18, 0}, {290, 4, 19, 0}, + {291, 4, 20, 0}, {292, 4, 21, 0} +}; + +void gpio_calc_eint_pos_bit(gpio_t gpio, u32 *pos, u32 *bit) +{ + uint32_t idx = gpio.id; + + *pos = 0; + *bit = 0; + + if (idx >= ARRAY_SIZE(eint_data)) + return; + + *pos = eint_data[idx][2] / MAX_EINT_REG_BITS; + *bit = eint_data[idx][2] % MAX_EINT_REG_BITS; +} + +struct eint_regs *gpio_get_eint_reg(gpio_t gpio) +{ + uint32_t idx = gpio.id; + void *addr; + + if (idx >= ARRAY_SIZE(eint_data)) + return NULL; + + switch (eint_data[idx][1]) { + case 0: + addr = (void *)EINT_E_BASE; + break; + case 1: + addr = (void *)EINT_S_BASE; + break; + case 2: + addr = (void *)EINT_W_BASE; + break; + case 3: + addr = (void *)EINT_N_BASE; + break; + case 4: + addr = (void *)EINT_C_BASE; + break; + default: + addr = NULL; + break; + } + + return addr; +}