[coreboot-gerrit] Change in coreboot[master]: mb/supermicro/x11ssh-tf: Relocate devicetree FSP settings

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43929 )

Change subject: mb/supermicro/x11ssh-tf: Relocate devicetree FSP settings
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mb/supermicro/x11ssh-tf: Relocate devicetree FSP settings

Also break the long SMBIOS slot description lines while we're at it.

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I10d577e4b9a59e3f4f954a8695ea2be017c87347
Signed-off-by: Angel Pons 
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
1 file changed, 11 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/43929/1

diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
index 6fa9772..2f37d86 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -11,19 +11,6 @@
    register "gen1_dec" = "0x007c0a01"	# Super IO SWC
    register "gen2_dec" = "0x000c0ca1"	# IPMI KCS

-	# PCIe configuration
-	# Enable JPCIE1
-	register "PcieRpEnable[0]" = "1"
-
-	# Enable ASpeed PCI bridge
-	register "PcieRpEnable[2]" = "1"
-
-	# Enable X550T (10GbE)
-	register "PcieRpEnable[4]" = "1"
-
-	# Enable M.2
-	register "PcieRpEnable[8]" = "1"
-
    # FIXME: find out why FSP crashes without this
    register "PchHdaVcType" = "Vc1"

@@ -66,22 +53,29 @@
    device domain 0 on
    	device pci 01.0 on end	# unused
    	device pci 01.1 on	# PCIE Slot (JPCIE1)
-			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
+			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort"
+					 "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
    	end
    	device pci 1c.0 on	# PCI Express Port 1 (Slot JPCIE1)
-			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
+			register "PcieRpEnable[0]" = "1"
+			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong"
+					 "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
    	end
    	device pci 1c.2 on	# PCI Express Port 3
+			register "PcieRpEnable[2]" = "1"
    		device pci 00.0 on	# Aspeed PCI Bridge
    			device pci 00.0 on end	# Aspeed 2400 VGA
    		end
    	end
-		device pci 1c.4 on	# PCI Express Port 5
+		device pci 1c.4 on	# PCI Express Port 5 (Intel X550T NIC)
+			register "PcieRpEnable[4]" = "1"
    		device pci 00.0 on end	# 10GbE
    		device pci 00.1 on end	# 10GbE
    	end
    	device pci 1d.0 on	# PCI Express Port 9
-			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
+			register "PcieRpEnable[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M.2 2280" "SlotDataBusWidth4X"
    	end
    	device pci 1f.0 on	# LPC Interface
    		chip drivers/ipmi