Shaunak Saha has uploaded a new change for review. ( https://review.coreboot.org/20006 )
Change subject: src/soc/intel/common: Modify smihandler calls as per common pmc code ......................................................................
src/soc/intel/common: Modify smihandler calls as per common pmc code
Change-Id: Iabadd80962324cf8de6a01d24aad25d257bcb048 Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/soc/intel/common/smihandler.c 1 file changed, 17 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/20006/1
diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c index 549a914..7fc089a 100644 --- a/src/soc/intel/common/smihandler.c +++ b/src/soc/intel/common/smihandler.c @@ -72,7 +72,7 @@
void southbridge_smi_set_eos(void) { - enable_smi(EOS); + pmc_enable_smi(EOS); }
struct global_nvs_t *smm_get_gnvs(void) @@ -133,7 +133,8 @@ uint8_t slp_typ;
/* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); + pmc_disable_smi(SLP_SMI_EN); + /* Figure out SLP_TYP */ reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); @@ -147,7 +148,7 @@ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
/* Clear pending GPE events */ - clear_gpe_status(); + pmc_clear_gpe_status();
/* Next, do the deed. */
@@ -168,7 +169,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */ - disable_all_gpe(); + pmc_disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; @@ -178,7 +179,7 @@ }
/* Clear the gpio gpe0 status bits in ACPI registers */ - clear_gpi_gpe_sts(); + pmc_clear_gpi_gpe_sts();
/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
@@ -187,7 +188,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - enable_pm1_control(SLP_EN); + pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ >= ACPI_S3) @@ -201,7 +202,7 @@ reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); + pmc_disable_pm1_control(SLP_EN | SLP_TYP); } }
@@ -266,11 +267,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); + pmc_disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); + pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_GNVS_UPDATE: @@ -302,7 +303,7 @@
void southbridge_smi_pm1(const struct smm_save_state_ops *save_state_ops) { - uint16_t pm1_sts = clear_pm1_status(); + uint16_t pm1_sts = pmc_clear_pm1_status();
/* * While OSPM is not active, poweroff immediately @@ -312,19 +313,19 @@ /* power button pressed */ if (IS_ENABLED(CONFIG_ELOG_GSMI)) elog_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + pmc_disable_pm1_control(-1UL); + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } }
void southbridge_smi_gpe0(const struct smm_save_state_ops *save_state_ops) { - clear_gpe_status(); + pmc_clear_gpe_status(); }
void southbridge_smi_tco(const struct smm_save_state_ops *save_state_ops) { - uint32_t tco_sts = clear_tco_status(); + uint32_t tco_sts = pmc_clear_tco_status();
/* Any TCO event? */ if (!tco_sts) @@ -340,7 +341,7 @@ { uint32_t reg32;
- reg32 = get_smi_en(); + reg32 = pmc_get_smi_en();
/* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) @@ -358,7 +359,7 @@ * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = clear_smi_status(); + smi_sts = pmc_clear_smi_status();
save_state_ops = get_smm_save_state_ops();