Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41690 )
Change subject: mb/ocp/deltalake: Config PCH PCIe ports ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41690/8/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/romstage.c:
https://review.coreboot.org/c/coreboot/+/41690/8/src/mainboard/ocp/deltalake... PS8, Line 72: for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { : mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = : dl_pch_pci_port[index].ForceEnable; : mupd->FspmConfig.PchPciePortLinkSpeed[dl_pch_pci_port[index].PortIndex] = : dl_pch_pci_port[index].PortLinkSpeed; : }
Can't this be done in the SoC code and pass this through the devicetree and via a config?
Hi Christian, for DeltaLake, the PCH PCIe configuration is same for all SKUs. So we choose the header file approach which is striaght forward. I suppose your suggestion is to define such in devicetree.cb instead. Is there a precedence of doing such? I think it is doable, but may be over-kill.