[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 208: 0
> Ok, looking back, TGL-U/Y seems to only has one CPU-side PCIe root port (00:06. […]

Yes, that's correct.  it's tide to 0.6.0 device and TGLU and TGLY only have 1 port(1x4).